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    Space-saving back-up power supply
    1.
    发明授权
    Space-saving back-up power supply 失效
    节省空间的备用电源

    公开(公告)号：US4645943A

    公开(公告)日：1987-02-24

    申请号：US660937

    申请日：1984-10-15

    Applicant: John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

    Inventor： John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

    IPC: G06F1/30 ,  H02J9/06 ,  H02J9/02

    CPC classification number: G06F1/30 ,  H02J9/061 ,  Y10T307/615 ,  Y10T307/625

    Abstract: A space-saving back-up power supply apparatus has length and width dimensions substantially the same as those of a conventional integrated circuit connector. The apparatus includes sockets arranged on its top for making connection to a socket-pluggable integrated circuit such as a standard CMOS RAM, and the apparatus has pins extending from its bottom for making connection to a printed circuit board or connector of a host electronic system. Control circuitry and one or more batteries are located within the apparatus. The back-up power supply is operative to provide power to the socket-pluggable integrated circuit even if the normal power supply of the host electronic system is short-circuited. The control circuitry of the back-up power supply controls the chip enable signal and performs a battery test upon power-up.

    Abstract translation: 节省空间的备用电源设备的长度和宽度尺寸基本上与传统的集成电路连接器相同。 该设备包括设置在其顶部的插座，用于连接到诸如标准CMOS RAM的插座可插拔集成电路，并且该设备具有从其底部延伸的引脚，用于连接到主机电子系统的印刷电路板或连接器。 控制电路和一个或多个电池位于设备内。 即使主机电子系统的正常电源短路，备用电源也可以为插座可插拔集成电路供电。 备用电源的控制电路控制芯片使能信号，并在上电时执行电池测试。

    Method and apparatus for extracting a predetermined pattern from a serial bit stream
    4.
    再颁专利
    Method and apparatus for extracting a predetermined pattern from a serial bit stream 失效

    公开(公告)号：USRE34241E

    公开(公告)日：1993-05-04

    申请号：US490801

    申请日：1990-03-08

    Applicant: Ching-Lin Jiang

    Inventor： Ching-Lin Jiang

    IPC: H04J3/06

    CPC classification number: H04J3/0605

    Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

    Temperature compensated monolithic delay circuit
    6.
    发明授权
    Temperature compensated monolithic delay circuit 失效
    温度补偿单片延迟电路

    公开(公告)号：US4843265A

    公开(公告)日：1989-06-27

    申请号：US217142

    申请日：1988-06-30

    Applicant: Ching-Lin Jiang

    Inventor： Ching-Lin Jiang

    IPC: G05F1/46

    CPC classification number: G05F1/466 ,  Y10S323/907

    Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

    Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

    Method and apparatus for extracting a predetermined bit pattern from a serial bit stream
    7.
    发明授权
    Method and apparatus for extracting a predetermined bit pattern from a serial bit stream 失效
    用于从串行位流中提取预定位模式的方法和装置

    公开(公告)号：US4730346A

    公开(公告)日：1988-03-08

    申请号：US13911

    申请日：1987-02-12

    Applicant: Ching-Lin Jiang

    Inventor： Ching-Lin Jiang

    IPC: H04J3/06 ,  H04L7/08

    CPC classification number: H04J3/0605

    Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

    Abstract translation: 通过将串行比特流的最后一位与串行比特流的预定数量的先前比特相组合来定位串行比特流中的嵌入的成帧位模式，该预定数量的串行比特流的先前比特间隔开成帧位的比特的间距 模式，并且测试这些位的组合以确定组合是否匹配成帧位模式的一部分。 如果没有发生匹配，则组合在一起的位被改变成不会导致匹配的位模式，当这些位（除了被忽略的最老位除外）被再次与串行的新位组合时 位流，无论新位的逻辑状态如何。 以这种方式，当它们到达并被组合和测试时，所有位将最终被改变，除了作为帧位模式的一部分的位之外。

    Data compression using content addressable memory
    8.
    发明授权
    Data compression using content addressable memory 失效
    使用内容可寻址内存的数据压缩

    公开(公告)号：US5339076A

    公开(公告)日：1994-08-16

    申请号：US876771

    申请日：1992-04-27

    Applicant: Ching-Lin Jiang

    Inventor： Ching-Lin Jiang

    IPC: G06F5/00 ,  G06F17/21 ,  G06T9/00 ,  H03M7/30 ,  H03M7/46

    CPC classification number: H03M7/3086 ,  G06T9/005

    Abstract: A data compression/decompression processor implements a modified Ziv-Lempel ("LZ") coding technique. The processor includes three modules, an interface, a coder-decoder ("CODEC"), and a MODEL. The CODEC and the MODEL modules together form compression engine, in which the CODEC provides variable length coding and data packing, and the MODEL implements the LZ processing. The MODEL uses content addressable memory ("CAM") in encoding mode for text storage and character matching, and uses CAM in decoding mode as an on-chip RAM to obtain high speed access.

    Abstract translation: 数据压缩/解压缩处理器实现修改的Ziv-Lempel（“LZ”）编码技术。 处理器包括三个模块，一个接口，一个编码器解码器（“CODEC”）和一个MODEL。 CODEC和MODEL模块一起形成压缩引擎，其中CODEC提供可变长度编码和数据打包，MODEL实现LZ处理。 MODEL在编码模式下使用内容可寻址存储器（“CAM”）进行文本存储和字符匹配，并将解码模式下的CAM用作片上RAM以获得高速访问。

    Delay circuit for a monolithic integrated circuit and method for adjusting delay of same
    9.
    发明授权
    Delay circuit for a monolithic integrated circuit and method for adjusting delay of same 失效
    单片集成电路的延迟电路及其延时调整方法

    公开(公告)号：US4894791A

    公开(公告)日：1990-01-16

    申请号：US828230

    申请日：1986-02-10

    Applicant: Ching-Lin Jiang ,  William J. Podkowa

    Inventor： Ching-Lin Jiang ,  William J. Podkowa

    IPC: H03K5/04 ,  H03K19/003

    CPC classification number: H03K5/04 ,  H03K19/00323

    Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable. A method for economically adjusting the delay of each of many like delay circuits embodied in a semiconductor wafer includes measuring a sample of the delays of the delay circuits, calculating an average delay, determining the difference between a desired delay and the average delay to determine an incremental amount of delay to eliminate or to add, determining from predetermined data which fusible links should be opened, and using a laser beam to open the appropriate links.

    Abstract translation: 可以在单片集成电路中实现的延迟电路包括多个电容器/激光可熔链节串联对。 相对于输入跃迁的电路的二进制输出信号的延迟与连接到电路中的电容量成正比。 因为激光熔丝可以选择性地用激光打开，连接到电路中的电容量可以逐渐减小; 因此，电路的延迟可以可调节到期望的值。 通过在延迟电路中包括多个导电元件/激光可熔链节串联对，电路的延迟也越来越可调。 用于经济地调节在半导体晶片中实现的许多类似延迟电路中的每一个的延迟的方法包括测量延迟电路的延迟的样本，计算平均延迟，确定期望延迟和平均延迟之间的差以确定 消除或添加的增量的延迟量，从预定数据确定哪个可熔断链接应该被打开，以及使用激光束打开适当的链接。

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