公开(公告)号：US10896137B2

公开(公告)日：2021-01-19

申请号：US16420629

申请日：2019-05-23

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Brent S. Haukness ,  Carl W. Werner

IPC: G06F12/02 ,  G06F12/14 ,  G06F21/44 ,  G06F21/55 ,  G06F21/75 ,  G06F21/79 ,  G06F3/06 ,  G11C13/00 ,  G11C7/24 ,  H04L9/00 ,  H04L9/08 ,  H04L9/32

Abstract: A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. In response to the request to perform the authentication operation, the authentication component may access the first data stored at the first non-volatile memory and the second data stored at the second non-volatile memory and determine whether the second data stored at the second non-volatile memory has become unreliable based on a memory disturbance condition. In response to determining that the second data stored at the second non-volatile memory has become unreliable, a corrective action associated with the first data stored at the first non-volatile memory may be performed.

公开(公告)号：US20170293575A1

公开(公告)日：2017-10-12

申请号：US15469999

申请日：2017-03-27

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Brent S. Haukness ,  Carl W. Werner

IPC: G06F12/14 ,  G06F3/06 ,  G06F21/62 ,  H04L9/32 ,  G06F21/79 ,  G06F21/64 ,  G11C13/00

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0679 ,  G06F12/0246 ,  G06F21/44 ,  G06F21/556 ,  G06F21/75 ,  G06F21/79 ,  G06F2212/202 ,  G11C7/24 ,  G11C13/0059 ,  H04L9/003 ,  H04L9/0894 ,  H04L9/321 ,  H04L9/3226

Abstract: A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. In response to the request to perform the authentication operation, the authentication component may access the first data stored at the first non-volatile memory and the second data stored at the second non-volatile memory and determine whether the second data stored at the second non-volatile memory has become unreliable based on a memory disturbance condition. In response to determining that the second data stored at the second non-volatile memory has become unreliable, a corrective action associated with the first data stored at the first non-volatile memory may be performed.

公开(公告)号：US09479176B1

公开(公告)日：2016-10-25

申请号：US14553364

申请日：2014-11-25

Applicant: Cryptography Research, Inc.

Inventor： John C. Eble, III ,  Scott C. Best ,  Hanson Quan

IPC: H03K19/177

CPC classification number: H03K19/17768

Abstract: A camouflage circuit instantiated on a semiconductor substrate includes a transient-comparison circuit that briefly expresses a value representative of either a one or a zero in dependence upon reference elements that are visibly indistinct from a perspective normal to the planar surface substrate surface, but that nevertheless exhibit distinct electrical responses. Transient comparisons that define logic states only briefly vastly complicate the use of reverse-engineering tools and techniques that rely on optical stimulation to sense when transistors are on or off.

Abstract translation: 在半导体衬底上实例化的伪装电路包括暂时比较电路，其根据从垂直于平面表面衬底表面的透视明显不明显的参考元件简要表示代表一个或零的值，但是仍然 表现出不同的电响应。 定义逻辑状态的瞬态比较只是简单地使使用反向工程工具和技术复杂化，这些工具和技术依赖于光学刺激来检测晶体管的导通或截止。

公开(公告)号：US20240211171A1

公开(公告)日：2024-06-27

申请号：US18531350

申请日：2023-12-06

Applicant: Cryptography Research, Inc.

Inventor： Winthrop John Wu ,  Bryan Wang ,  Marufa Kaniz ,  Guilherme Ozari de Almeida ,  Scott C. Best

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0619 ,  G06F3/0679

Abstract: A request to perform a memory operation addressed to a first address corresponding to a first logical unit of logical units of a memory is received. Address mask data that corresponds to the logical units is identified. Multiple transformed addresses are determined using the first address and the address mask data. The transformed addresses can include a target address corresponding to the first logical unit and additional addresses corresponding to other logical units. The memory operation is performed at the target address corresponding to the first logical unit and dummy memory operations are performed at the additional addresses corresponding to the additional logical units.

公开(公告)号：US11868512B2

公开(公告)日：2024-01-09

申请号：US17636831

申请日：2020-09-04

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best ,  Christopher Leigh Rodgers

IPC: G06F21/40 ,  G06F21/76

CPC classification number: G06F21/76

Abstract: A pattern detector circuit is provided in a security chip, wherein the pattern detector circuit monitors accesses of a plurality of configuration registers, each of the plurality of configuration registers having a corresponding address. In response to receiving from a host a predefined sequence of accesses of the plurality of configuration registers for one or more operations to the plurality of configuration registers, a processor in the pattern detector circuit determines a value indicative of a current version of a netlist for the security chip. The determined value is made available to be obtained by a read operation by the host at a specific configuration register address.

公开(公告)号：US11797718B2

公开(公告)日：2023-10-24

申请号：US17633534

申请日：2020-08-21

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Scott C. Best

IPC: G06F21/00 ,  G06F21/87

CPC classification number: G06F21/87

Abstract: A resistor mesh with distributed sensing points is provided in a security chip as an anti-tamper shield. An analog multiplexing circuit is configured to receive a pair of digital selection values created by an algorithm processing circuit, and produce a respective differential voltage formed by a pair of voltages obtained at a pair of selected sensing points within the resistor mesh corresponding to the pair of digital selection values. Each differential voltage is converted into a corresponding digital output value. An algorithm processing circuit is configured to receive a respective digital output value associated with each pair of digital selection values and derive a binary value based on a subset of the digital output values, wherein the binary value is unique to the security chip.

公开(公告)号：US11677571B2

公开(公告)日：2023-06-13

申请号：US16466146

申请日：2017-11-30

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: H04L9/32 ,  G06F21/73 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G06F21/73 ,  H04L9/0866 ,  H04L2209/12

Abstract: A physically unclonable function circuit (PUF) is used to generate a fingerprint value based on the uniqueness of the physical characteristics (e.g., resistance, capacitance, connectivity, etc.) of a tamper prevention (i.e., shielding) structure that includes through-silicon vias and metallization on the backside of the integrated circuit. The physical characteristics depend on random physical factors introduced during manufacturing. This causes the chip-to-chip variations in these physical characteristics to be unpredictable and uncontrollable which makes more difficult to duplicate, clone, or modify the structure without changing the fingerprint value. By including the through-silicon vias and metallization on the backside of the integrated circuit as part of the PUF, the backside of the chip can be protected from modifications that can be used to help learn the secure cryptographic keys and/or circumvent the secure cryptographic (or other) circuitry.

公开(公告)号：US20230137364A1

公开(公告)日：2023-05-04

申请号：US17984155

申请日：2022-11-09

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/08

Abstract: The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.

公开(公告)号：US20210271542A1

公开(公告)日：2021-09-02

申请号：US16972560

申请日：2019-06-05

Applicant: Cryptography Research, Inc.

Inventor： Mark Evan Marson ,  Scott C. Best ,  Helena Handschuh ,  Winthrop John Wu

IPC: G06F11/10 ,  H04L9/32 ,  H04L9/08

Abstract: A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.

公开(公告)号：US20190012146A1

公开(公告)日：2019-01-10

申请号：US16115917

申请日：2018-08-29

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best

IPC: G06F7/58

Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.