公开(公告)号：US10691633B2

公开(公告)日：2020-06-23

申请号：US16421211

申请日：2019-05-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  H03K3/38 ,  G06N10/00 ,  G06F15/76 ,  B82Y10/00 ,  H04L29/08

Abstract: Methods and systems for solving various computational problems with quantum processors are provided. Such quantum processors comprise a plurality of quantum devices together with a plurality of coupling devices. The quantum processor is initialized by setting states of the quantum devices and coupling devices and allowed to evolve to a final state which approximates a natural ground state of the computational problem. The final state can include values of nodes arranged in a lattice in the quantum processor and can represent a solution to the computational processor. The computational problem can have complexity P, NP, NP-Hard, or NP-Complete and may be mapped to a quantum processor with nearest-neighbor and next-nearest-neighbor couplings. The solution to the computational problem can be read out from the quantum processor and transmitted as a data signal embodied in a carrier wave.

公开(公告)号：US09727527B2

公开(公告)日：2017-08-08

申请号：US14727521

申请日：2015-06-01

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/76 ,  H03K19/195 ,  H03K3/38 ,  H04L29/08 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US09405876B2

公开(公告)日：2016-08-02

申请号：US14186895

申请日：2014-02-21

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

公开(公告)号：US09069928B2

公开(公告)日：2015-06-30

申请号：US14175731

申请日：2014-02-07

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: H03K19/195 ,  G06F15/76 ,  H03K3/38 ,  B82Y10/00 ,  G06N99/00

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US20210342289A1

公开(公告)日：2021-11-04

申请号：US17355458

申请日：2021-06-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H.S. Amin ,  Geordie Rose ,  David Grant ,  Miles F.H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  H03K3/38 ,  H04L29/08 ,  G06N10/00 ,  G06F15/76

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US11093440B2

公开(公告)日：2021-08-17

申请号：US16859672

申请日：2020-04-27

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  H03K3/38 ,  H04L29/08 ,  G06N10/00 ,  G06F15/76 ,  B82Y10/00

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US10346349B2

公开(公告)日：2019-07-09

申请号：US16173846

申请日：2018-10-29

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  G06N99/00 ,  G06F15/76 ,  H03K3/38 ,  H04L29/08 ,  G06N10/00 ,  B82Y10/00

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US20150332164A1

公开(公告)日：2015-11-19

申请号：US14727521

申请日：2015-06-01

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H.S. Amin ,  Geordie Rose ,  David Grant ,  Miles F.H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06N99/00 ,  H04L29/08 ,  H03K3/38

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US09026574B2

公开(公告)日：2015-05-05

申请号：US13678266

申请日：2012-11-15

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06G7/32 ,  G06F17/00 ,  G06N5/00 ,  G06F17/10 ,  G06F17/11 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/10 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。

公开(公告)号：US20140229705A1

公开(公告)日：2014-08-14

申请号：US14175731

申请日：2014-02-07

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/76

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract translation: 提供了用于解决各种计算问题的模拟处理器。 这种模拟处理器包括与多个耦合装置一起布置成格子的多个量子器件。 模拟处理器进一步包括偏置控制系统，每个偏置控制系统被配置为在对应的量子器件上施加局部有效偏置。 多个耦合装置中的一组耦合装置被配置为耦合格子中的最近邻量子器件。 另一组耦合器件配置成耦合下一个最近邻量子器件。 模拟处理器还包括多个耦合控制系统，每个耦合控制系统被配置为将多个耦合装置中的对应耦合装置的耦合值调谐到耦合。 这种量子处理器还包括一组读出装置，每个读出装置被配置为从多个量子器件中的对应的量子器件测量信息。