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11.发明申请METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING 有权使用电流感测感知非挥发性储存中的负压阈值电压的方法公开(公告)号：US20080247238A1
公开(公告)日：2008-10-09
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/06 , G11C11/4091
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译： 在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。 控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。 即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。 通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。
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公开(公告)号：US20080158960A1
公开(公告)日：2008-07-03
申请号：US11618791
申请日：2006-12-30
IPC分类号： G11C29/00
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
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13.发明申请Reducing Energy Consumption When Applying Body Bias To Substrate Having Sets Of Nand Strings 有权降低能量消耗时，应用身体偏倚衬底有一套Nand弦公开(公告)号：US20110267887A1
公开(公告)日：2011-11-03
申请号：US13178853
申请日：2011-07-08
IPC分类号： G11C16/10
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
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14.发明授权Applying different body bias to different substrate portions for non-volatile storage 有权将不同的体偏置应用于不同的衬底部分用于非易失性存储公开(公告)号：US08000146B2
公开(公告)日：2011-08-16
申请号：US12759581
申请日：2010-04-13
IPC分类号： G11C16/04
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
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15.发明授权Applying adaptive body bias to non-volatile storage based on number of programming cycles 有权基于编程周期数将适应性体偏置应用于非易失性存储公开(公告)号：US07751244B2
公开(公告)日：2010-07-06
申请号：US12335803
申请日：2008-12-16
IPC分类号： G11C16/04
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
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公开(公告)号：US07606072B2
公开(公告)日：2009-10-20
申请号：US11739509
申请日：2007-04-24
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。
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公开(公告)号：US07583539B2
公开(公告)日：2009-09-01
申请号：US11618786
申请日：2006-12-30
IPC分类号： G11C16/04
CPC分类号： G11C7/04 , G11C11/5621 , G11C16/0483 , G11C16/30
摘要： A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.
摘要翻译： 一种非易失性存储系统，其中主体偏置被施加到非易失性存储系统以补偿阈值电压，子阈值斜率，耗尽层宽度和/或1 / f噪声的温度相关变化。 基于温度依赖参考信号设置期望的偏置电平。 在一种方法中，当温度升高时，偏置的水平可以降低。 可以通过向基板的p阱和n阱施加电压来施加主体偏置，在将n阱接地的同时向p阱施加电压，或者接地主体并向源施加电压，并且 /或一组非易失性存储元件的漏极。 此外，在程序，读取或验证操作期间，可以将非依赖于温度的和/或温度依赖的电压施加到非易失性存储系统中的选定和未选择的字线。 温度依赖电压可以根据不同的温度系数而变化。
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公开(公告)号：US07583535B2
公开(公告)日：2009-09-01
申请号：US11618782
申请日：2006-12-30
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C7/04 , G11C11/5621 , G11C16/10 , G11C16/3454 , G11C29/00 , G11C2211/5644 , G11C2211/565
摘要： A body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.
摘要翻译： 身体偏压被施加到非易失性存储系统以补偿阈值电压，子阈值斜率，耗尽层宽度和/或1 / f噪声的温度依赖性变化。 基于温度依赖参考信号设置期望的偏置电平。 在一种方法中，当温度升高时，偏置的水平可以降低。 可以通过向基板的p阱和n阱施加电压来施加主体偏置，在将n阱接地的同时向p阱施加电压，或者接地主体并向源施加电压，并且 /或一组非易失性存储元件的漏极。 此外，在程序，读取或验证操作期间，可以将非依赖于温度的和/或温度依赖的电压施加到非易失性存储系统中的选定和未选字线。 温度依赖电压可以根据不同的温度系数而变化。
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公开(公告)号：US07468920B2
公开(公告)日：2008-12-23
申请号：US11618791
申请日：2006-12-30
CPC分类号： G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
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20.发明申请公开(公告)号：US20080239824A1
公开(公告)日：2008-10-02
申请号：US11693616
申请日：2007-03-29
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.
摘要翻译： 由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。 以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。 这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。 在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被设置为第一电压，并且存储器平面的后半部分中的位线远离字源 线电压被设定为第二电压。
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