-
公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
-
公开(公告)号：US07551468B2
公开(公告)日：2009-06-23
申请号：US12060992
申请日：2008-04-02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
-
公开(公告)号：US20080177942A1
公开(公告)日：2008-07-24
申请号：US12060998
申请日：2008-04-02
IPC分类号： G06F12/00
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
-
公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。 处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
-
公开(公告)号：US20080183957A1
公开(公告)日：2008-07-31
申请号：US12060992
申请日：2008-04-02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
-
公开(公告)号：US20100005335A1
公开(公告)日：2010-01-07
申请号：US12165858
申请日：2008-07-01
CPC分类号： G06F11/2007
摘要： A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 一种处理设备，系统，方法和设计结构，用于提供具有动态段保存和修复的微处理器接口。 处理装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
-
公开(公告)号：US07440531B2
公开(公告)日：2008-10-21
申请号：US11055865
申请日：2005-02-11
IPC分类号： H04L25/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wrap around eye tracking.
摘要翻译： 公开了一种用于使在弹性接口总线上接收的数字数据去偏斜和对准的方法和装置。 在接收到数据后，通过可编程延迟线发送。 在可编程延迟线中，数据在数据眼图中的三个点进行采样。 动态调整三个采样点，以最大化数据眼图的覆盖范围。 在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在采样器中的延迟调整时从功能采样器采样。 在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。 所述方法和装置允许替代眼睛跟踪并包裹眼睛跟踪。
-
18.发明申请公开(公告)号：US20140032799A1
公开(公告)日：2014-01-30
申请号：US13561446
申请日：2012-07-30
IPC分类号： G06F13/00
CPC分类号： G06F15/17318 , G06F9/00 , G06F11/3058 , G06F13/00 , G06F13/1673 , G06F13/24 , G06F13/4217 , G06F13/4282 , G06F15/803 , G06F19/00 , H04B1/38 , H04L12/56 , Y02D10/14 , Y02D10/151
摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
摘要翻译： 可校准通信链路包括多条平行线。 由自动机制确定的动态变量和/或可中断间隔进行校准。 校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据 可能的最小的设备功能中断，如低活动水平所示。 此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。
-
公开(公告)号：US08082474B2
公开(公告)日：2011-12-20
申请号：US12165799
申请日：2008-07-01
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。 此外，阴影比较逻辑用于将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较阴影计数器用于计算相对于总线错误的误比率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
-
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
-
-
-
-
-
-
-
-
-
搜索结果
90 条记录 (耗时 0.039 秒)
