公开(公告)号：US20150003281A1

公开(公告)日：2015-01-01

申请号：US13927523

申请日：2013-06-26

申请人： William C. Hasenplaugh ,  Tryggve Fossum ,  Judson S. Leonard

发明人： William C. Hasenplaugh ,  Tryggve Fossum ,  Judson S. Leonard

IPC分类号： H04L12/933 ,  H04L12/24 ,  H04L12/733

CPC分类号： H04L49/15 ,  H04L41/12 ,  H04L45/12 ,  H04L45/122 ,  H04L49/101 ,  H04L49/25

摘要： Architectures, apparatus and systems employing scalable multi-layer 2D-mesh routers. A 2D router mesh comprises bi-direction pairs of linked paths coupled between pairs of IO interfaces and configured in a plurality of rows and columns forming a 2D mesh. Router nodes are located at the intersections of the rows and columns, and are configured to forward data units between IO inputs and outputs coupled to the mesh at its edges through use of shortest path routes defined by agents at the IO interfaces. Multiple instances of the 2D meshes may be employed to support bandwidth scaling of the router architecture. One implementation of a multi-layer 2D mesh is built using a standard tile that is tessellated to form a 2D array of standard tiles, with each 2D mesh layer offset and overlaid relative to the other 2D mesh layers. IO interfaces are then coupled to the multi-layer 2D mesh via muxes/demuxes and/or crossbar interconnects.

摘要翻译： 采用可扩展多层二维网状路由器的架构，设备和系统。 2D路由器网格包括耦合在IO对接口之间的双向对链接路径，并且被配置成形成2D网格的多个行和列。 路由器节点位于行和列的交点处，并且被配置为通过使用由IO接口上的代理定义的最短路径路由来在IO输入和耦合到其边缘的网格的输出之间转发数据单元。 可以采用2D网格的多个实例来支持路由器架构的带宽缩放。 使用被镶嵌的标准瓦片来构建多层2D网格的一个实施方式，以形成标准瓦片的2D阵列，其中每个2D网格层相对于其他2D网格层偏移并重叠。 然后，IO接口通过多路复用/解复用和/或交叉连接互连到多层2D网格。

公开(公告)号：US08190863B2

公开(公告)日：2012-05-29

申请号：US10884359

申请日：2004-07-02

申请人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

发明人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F13/00 ,  G06F13/28 ,  G06F1/00

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22

摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

摘要翻译： 一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。 在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。 一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。 在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。 在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。 描述和要求保护其他实施例。

公开(公告)号：US07380169B2

公开(公告)日：2008-05-27

申请号：US10948904

申请日：2004-09-24

申请人： Tryggve Fossum ,  Yaron Shragai ,  Ugonna Echeruo ,  Shubhendu S. Mukherjee

发明人： Tryggve Fossum ,  Yaron Shragai ,  Ugonna Echeruo ,  Shubhendu S. Mukherjee

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/3824 ,  G06F9/3861 ,  G06F11/0715 ,  G06F11/1016 ,  G06F11/1032

摘要： An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.

摘要翻译： 一种装置包括收集与一个或多个处理相关联的存储指令信息的缓冲器。 收集的存储指令信息包括要存储数据的数据和地址。 该装置还包括缓冲器控制，其在收集与第二进程相关联的存储指令之前，将与第一进程相关联的存储指令的缓冲器排出。

公开(公告)号：US07370231B2

公开(公告)日：2008-05-06

申请号：US11012979

申请日：2004-12-14

申请人： Tryggve Fossum ,  Yaron Shragai ,  Shubhendu S. Mukherjee

发明人： Tryggve Fossum ,  Yaron Shragai ,  Shubhendu S. Mukherjee

IPC分类号： G06F11/00

CPC分类号： G06F11/0721 ,  G06F11/0793

摘要： An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.

摘要翻译： 处理器的错误处理程序，响应于处理器的第一检测到的不可恢复错误（DUE）执行，响应于通过评估第二DUE对错误处理例程的正确性的影响而发生第二DUE的指示 。

公开(公告)号：US5829051A

公开(公告)日：1998-10-27

申请号：US223069

申请日：1994-04-04

申请人： Simon C. Steely, Jr. ,  Richard B. Gillett, Jr. ,  Tryggve Fossum

发明人： Simon C. Steely, Jr. ,  Richard B. Gillett, Jr. ,  Tryggve Fossum

IPC分类号： G06F12/08 ,  G06F9/26

CPC分类号： G06F12/0864

摘要： An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.

摘要翻译： 一种用于向高速缓存提供数据并从其中检索数据的装置包括耦合在处理器和存储器之间的存储器子系统，以便将存储器数据快速地存取到处理器。 存储器子系统包括高速缓冲存储器。 提供给存储器子系统的地址被划分为高速缓存索引和标签，并且高速缓存索引被散列以提供用于访问高速缓存的多个替代地址。 在缓存读取期间，选择每个备选地址以响应于在该位置处的数据的有效性的指示符来搜索数据。 替代地址的选择可以通过具有对应于替代地址的数量的位数的掩码来完成。 每个位指示在缓存访问期间是否应该使用该位置处的替代地址来搜索数据。 或者，具有比高速缓存具有更多条目的存储器装置可以用于存储用于定位数据的最佳替代地址的选择值。 基于修改的最近最少使用的技术将数据分配给每个备选地址，其中使用量子数和模数计数器来对数据进行时间戳。

公开(公告)号：US5113521A

公开(公告)日：1992-05-12

申请号：US638149

申请日：1991-01-09

申请人： Francis X. McKeen ,  Tryggve Fossum ,  Dileep P. Bhandarkar ,  Cheryl A. Wiecek

发明人： Francis X. McKeen ,  Tryggve Fossum ,  Dileep P. Bhandarkar ,  Cheryl A. Wiecek

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at this time, however. Any other vector instructions executing simutaneously with the faulting vector instruction are allowed to continue so long as those instructions do not require data from the faulting instruction. The faulting partially completed vector instruction resumes execution after the operating system has processed the memory management exception.

摘要翻译： 数据处理系统通过停止异常发生时执行的故障向量指令的执行，并且通过设置向量处理器的状态信息来确认异常的存在来处理由矢量处理器中的故障向量指令引起的存储器管理异常 并且包括关于当异常发生时正在执行的向量指令的子程序的信息。 然而，标量处理器此时不会中断。 只要这些指令不需要来自故障指令的数据，允许与故障向量指令同时执行的任何其他向量指令。 故障部分完成向量指令在操作系统处理内存管理异常后恢复执行。

公开(公告)号：US08799902B2

公开(公告)日：2014-08-05

申请号：US11786019

申请日：2007-04-09

申请人： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

发明人： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

IPC分类号： G06F9/46 ,  G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F15/173

CPC分类号： G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

摘要翻译： 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

公开(公告)号：US08244980B2

公开(公告)日：2012-08-14

申请号：US11472877

申请日：2006-06-21

申请人： Tryggve Fossum

发明人： Tryggve Fossum

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/084

摘要： A method and apparatus for improving shared cache performance. In one embodiment, the present invention includes a cache having multiple ways. A locality tester measures a first locality of a first process and second locality of a second process. A first set of multiple ways stores the data used by the first process and a second set of multiple ways stores the data used by the second process, where the second set is a superset of the first set.

摘要翻译： 一种用于提高共享缓存性能的方法和装置。 在一个实施例中，本发明包括具有多种方式的高速缓存。 地点测试者测量第一进程的第一地点和第二进程的第二地点。 第一组多路存储第一过程使用的数据，第二组多路存储由第二过程使用的数据，其中第二集合是第一集合的超集。

公开(公告)号：US20080250415A1

公开(公告)日：2008-10-09

申请号：US11786019

申请日：2007-04-09

申请人： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

发明人： Ramesh Kumar Illikkal ,  Ravishankar Iyer ,  Jaideep Moses ,  Don Newell ,  Tryggve Fossum

IPC分类号： G06F9/46

CPC分类号： G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

摘要翻译： 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

公开(公告)号：US06675192B2

公开(公告)日：2004-01-06

申请号：US10293975

申请日：2002-11-11

申请人： Joel S. Emer ,  Rebecca L. Stamm ,  Bruce E. Edwards ,  Matthew H. Reilly ,  Craig B. Zilles ,  Tryggve Fossum ,  Christopher F. Joerg ,  James E. Hicks, Jr.

发明人： Joel S. Emer ,  Rebecca L. Stamm ,  Bruce E. Edwards ,  Matthew H. Reilly ,  Craig B. Zilles ,  Tryggve Fossum ,  Christopher F. Joerg ,  James E. Hicks, Jr.

IPC分类号： G06F948

CPC分类号： G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/485 ,  G06F9/526 ,  Y02D10/24

摘要： Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

摘要翻译： 当程序正在等待一个或多个事件发生时，程序在同步多线程处理器中的指令的执行是通过在手臂指令上首先布防事件监视器来进行的，也就是识别事件监视器要监视的一个或多个事件 ，例如对所识别的存储器位置或一组位置的值或状态的修改，以及设置监视标志以指示启用事件监视器。 在执行静默请求指令时，如果设置了监视标志，并且启动了定时器，则该程序静止。 在通过事件监视器对所识别的事件进行观察时，或者在定时器到期时，清除监视标志并重新执行程序。