公开(公告)号：US08028195B2

公开(公告)日：2011-09-27

申请号：US12114070

申请日：2008-05-02

申请人： Darren Anand ,  John A. Fifield ,  Kevin W. Gorman

发明人： Darren Anand ,  John A. Fifield ,  Kevin W. Gorman

IPC分类号： G06F11/00

CPC分类号： G01R31/31721 ,  G06F17/505 ,  G06F2217/78

摘要： A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于指示具有多个电源的片上电源系统的状态的系统，具有用于接收数字符合性信号的电力系统状态寄存器，与 多个电源中的一个并且具有相关联的合规级别，其中每个数字符合信号指示其相关联的电源是否在相关联的合规级别操作，并且其中电力系统状态寄存器基于数字信号产生电源状态信号 指示数字符合信号状态的符合性信号; 以及用于输出电源状态信号的输出，其中如果电源正在其相关联的顺应性水平下操作，则电源状态信号指示电源正在通过，否则电源状态信号指示电源发生故障 。

公开(公告)号：US20070046361A1

公开(公告)日：2007-03-01

申请号：US11161966

申请日：2005-08-24

申请人： Darren Anand ,  Larry Wissel

发明人： Darren Anand ,  Larry Wissel

IPC分类号： H01H37/76

CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.

摘要翻译： 电路包括用于提供用于控制编程晶体管（212）的栅极的可变栅极信号（220）的电压控制器（224），其与编程集成电路的电可编程熔丝（“eFuse”）（204）一起使用 （200）。 电压控制器根据电路是否处于eFuse编程模式或eFuse电阻测量模式来调节门信号。 电压控制器可以可选地包括用于调谐门信号的电压调谐器（252），以解决由制造变化引起的编程晶体管的工作变化。

公开(公告)号：US20050007866A1

公开(公告)日：2005-01-13

申请号：US10604184

申请日：2003-06-30

申请人： Darren Anand ,  John Fifield ,  Harold Pilo

发明人： Darren Anand ,  John Fifield ,  Harold Pilo

IPC分类号： G11C29/02 ,  G11C8/00

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/1204

摘要： A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.

摘要翻译： 一种用于定时在eDRAM中预充电期间开始的方法和电路。 该电路包括：延迟锁定环电路，用于接收时钟信号并产生用于调整时钟信号的内部延迟的控制信号; 以及用于响应于控制信号产生延迟的时钟信号的装置。 用于产生延迟时钟信号的装置是多级延迟电路，多级延迟级电路的每级串联连接，每级分别响应控制信号。

公开(公告)号：US07512915B2

公开(公告)日：2009-03-31

申请号：US11739819

申请日：2007-04-25

申请人： Darren Anand ,  Nazmul Habib ,  Robert McMahon ,  Troy Perry

发明人： Darren Anand ,  Nazmul Habib ,  Robert McMahon ,  Troy Perry

IPC分类号： G06F17/50

CPC分类号： H01L22/34 ,  G06F2217/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.

摘要翻译： 在机器可读介质中实例化的设计结构; 设计结构包括用于设计测试电路的所有必要信息。 测试电路用于执行特定于设备的测试，并在集成电路（例如ASIC）上获取参数数据，使得每个芯片单独测试，而不需要过多的测试时间要求，附加的硅或特殊的测试设备。 该设计结构包括至少一个测试电路，并且可以集成到IC设计中，以及用于产生最终设计结构的所有所需的制造数据。 最终设计结构可以是GDS存储介质或适于将最终数据结构发送到例如制造商，代工厂，客户或其他设计公司的另一种形式的介质。

公开(公告)号：US20050120270A1

公开(公告)日：2005-06-02

申请号：US10707071

申请日：2003-11-19

申请人： Darren Anand ,  Kevin Gorman ,  Michael Nelms

发明人： Darren Anand ,  Kevin Gorman ,  Michael Nelms

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/14 ,  G11C29/56008 ,  G11C2029/5604

摘要： A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.

摘要翻译： 位故障映射电路通过利用从低速自动测试设备（ATE）测试器产生的高速倍增时钟，精确地生成诸如DRAM的嵌入式存储器的位故障映射。 该电路在ATE测试仪，被测嵌入式内存，内置自检（BIST）和内置冗余分析（BIRA）之间进行通信。 通过在遇到失败时暂停BIST测试电路，即BIST预期数据与从阵列读取的实际数据之间的不匹配，然后移位位故障数据，提供嵌入式DRAM存储器的精确位故障映射 使用低速ATE测试仪时钟关闭芯片。 此后，通过使用高速内部时钟再次运行BIST，从故障点恢复高速测试，以提供高速位Fail Map。

公开(公告)号：US20080030260A1

公开(公告)日：2008-02-07

申请号：US11872273

申请日：2007-10-15

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： H01H37/76

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

公开(公告)号：US20080025071A1

公开(公告)日：2008-01-31

申请号：US11868046

申请日：2007-10-05

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： G11C11/00

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

摘要翻译： 用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻 尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。

公开(公告)号：US20050104639A1

公开(公告)日：2005-05-19

申请号：US10707067

申请日：2003-11-19

申请人： Darren Anand ,  Kevin Gorman

发明人： Darren Anand ,  Kevin Gorman

IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C11/407 ,  H03L7/00 ,  H03L7/06 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/16

CPC分类号： H03L7/07 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814

摘要： A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.

摘要翻译： 一种能够产生多个多相时钟信号的模块化数字锁定环（DLL）架构，其特别适用于具有片上定时的嵌入式DRAM系统的同步。 该架构包括单核频率锁定电路，其包括具有控制逻辑的延迟元件和能够将DLL系统时钟频率锁定到外部参考时钟的锁定电路，以及能够使多个内部时钟同步的多个次级锁相电路 信号到外部参考时钟的任何相位。