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    Selective post-doping of gate structures by means of selective oxide growth
    12.
    发明申请
    Selective post-doping of gate structures by means of selective oxide growth 失效
    通过选择性氧化物生长选择性地掺杂栅极结构

    公开(公告)号：US20060057811A1

    公开(公告)日：2006-03-16

    申请号：US11268100

    申请日：2005-11-07

    申请人： Anthony Chou ,  Toshiharu Furukawa ,  Steven Holmes

    发明人： Anthony Chou ,  Toshiharu Furukawa ,  Steven Holmes

    IPC分类号： H01L21/336 ,  H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/266 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

    摘要翻译： 提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。 本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。 可以使用常规图案化在单个基板上处理多个栅极区域。 在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

    Body contact structures and methods of manufacturing the same
    13.
    发明授权
    Body contact structures and methods of manufacturing the same 有权
    身体接触结构及其制造方法

    公开(公告)号：US08053325B1

    公开(公告)日：2011-11-08

    申请号：US12782320

    申请日：2010-05-18

    申请人： Anthony Chou ,  Arvind Kumar ,  Shreesh Narasimha

    发明人： Anthony Chou ,  Arvind Kumar ,  Shreesh Narasimha

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78615 ,  H01L29/66772

    摘要： A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.

    摘要翻译： 减少寄生电容并改善器件的体电阻和制造方法的体接触结构。 该方法包括在基板上形成栅极绝缘体材料和栅电极材料。 该方法还包括图案化栅极绝缘体材料和栅电极材料以形成具有与第二部分隔离的第一部分的形状的栅极结构。 该方法还包括在第一部分的侧面上形成源极和漏极区域，在第二部分的侧面和下面区域形成体接触，以及在隔离第一部分与第二部分的第二部分的空间内形成层间电介质 栅极结构，以及栅极结构，源极和漏极区域以及身体接触。

    Selective post-doping of gate structures by means of selective oxide growth
    15.
    发明申请
    Selective post-doping of gate structures by means of selective oxide growth 失效
    通过选择性氧化物生长选择性地掺杂栅极结构

    公开(公告)号：US20050148144A1

    公开(公告)日：2005-07-07

    申请号：US10732657

    申请日：2003-12-10

    申请人： Anthony Chou ,  Toshiharu Furukawa ,  Steven Holmes

    发明人： Anthony Chou ,  Toshiharu Furukawa ,  Steven Holmes

    IPC分类号： H01L21/266 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/266 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

    摘要翻译： 提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。 本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。 可以使用常规图案化在单个基板上处理多个栅极区域。 在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。