公开(公告)号：US20090288160A1

公开(公告)日：2009-11-19

申请号：US12122484

申请日：2008-05-16

申请人： James Lyall Esliger ,  Denis Foley

发明人： James Lyall Esliger ,  Denis Foley

IPC分类号： H04L9/32

CPC分类号： G06F21/572 ,  G06F21/575

摘要： An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

摘要翻译： 集成电路（100）可以经由调试访问端口（105）接收引导加载程序代码（114），其中启动逻辑可操作以在可编程处理器（103）的复位（123）从调试访问 端口（105），命令和来自调试访问端口的可编程处理器，同时仍然允许复位（123）命令，同时允许对存储器（112）的写访问以接收写入存储器的引导加载程序代码映像（114） 112）。 引导逻辑还从调试访问端口阻止对存储器子系统（109）的命令，并且在允许写入引导加载程序代码映像（114）之后，关闭对存储器（112）的写访问。 启动逻辑通过执行安全检查来验证引导加载程序代码映像（114），并且如果它有效则跳转到引导加载程序代码映像（114），从而允许其在可编程处理器（103）上运行。 引导逻辑可以是逻辑电路，软件或其组合。

公开(公告)号：US20090287895A1

公开(公告)日：2009-11-19

申请号：US12121573

申请日：2008-05-15

申请人： Denis Foley ,  Aris Balatsos

发明人： Denis Foley ,  Aris Balatsos

IPC分类号： G06F12/14 ,  G06F13/28

CPC分类号： G06F12/1433 ,  G06F21/79 ,  G06F21/85

摘要： A secure memory access system includes a memory control module, at least one direct memory access module, and a plurality of input/output interface modules. The direct memory access module is operative to transfer information between all of the input/output interface modules and the memory control module in response to transfer configuration information.

摘要翻译： 安全存储器访问系统包括存储器控制模块，至少一个直接存储器访问模块和多个输入/输出接口模块。 直接存储器访问模块可操作以响应于传送配置信息在所有输入/输出接口模块和存储器控制模块之间传送信息。

公开(公告)号：US20090307411A1

公开(公告)日：2009-12-10

申请号：US12133173

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F1/12

CPC分类号： G01R31/318555 ,  G11C7/24 ,  G11C29/12 ,  G11C29/14 ,  G11C2029/3202

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 确保存储在存储在ROM和/或PROM中的寄存器或锁存器，RAM和/或永久机密中的临时秘密。 用于保护IC上的信息的一个实施例包括响应于进入测试操作模式并在接收到测试模式命令之前进入测试模式并重置每个寄存器。 集成电路实施例包括测试控制逻辑，其可操作以将集成电路配置为测试模式并且在测试模式期间控制集成电路，一组寄存器以及耦合到测试控制逻辑的功能复位控制器 一组寄存器，用于从测试控制逻辑接收复位命令，并响应于进入测试模式的命令向该组寄存器提供复位命令。

公开(公告)号：US20090289615A1

公开(公告)日：2009-11-26

申请号：US12123731

申请日：2008-05-20

申请人： Denis Foley

发明人： Denis Foley

IPC分类号： G05B24/02

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

摘要翻译： 集成电路包括能量控制器，其基于集成电路的期望目标频率值生成用于集成电路的电源电压电平。 能量控制器基于电源电压电平来配置可编程硬件过程传感器，使得可编程硬件过程传感器能够在以电源电压电平操作时模拟与集成电路相关联的预定关键路径的电特性。 通过在一段时间内监视可编程硬件过程传感器的频率，能量控制器可以将监控的频率与预期值进行比较，并确定电源电压电平是否可以被调整，还是应该保持。

公开(公告)号：US07345239B2

公开(公告)日：2008-03-18

申请号：US10732975

申请日：2003-12-11

申请人： Philip Tousignant ,  Denis Foley ,  Robert M. Mondor

发明人： Philip Tousignant ,  Denis Foley ,  Robert M. Mondor

IPC分类号： H02G3/04

CPC分类号： H02G3/0437 ,  H02G3/32

摘要： One disclosed system comprises a first channel for routing at least one of a plurality of cables in a first direction; a second channel for routing said at least one cable in a second direction; and a plurality of teeth spaced apart from one another and disposed in one of said first channel and said second channel, said teeth positioned to create spaces in-between said plurality of cables before said at least one cable transitions from said first direction to said second direction.

摘要翻译： 一个公开的系统包括用于沿第一方向路由多个电缆中的至少一个的第一通道; 用于沿第二方向布置所述至少一个电缆的第二通道; 以及多个彼此间隔开并设置在所述第一通道和所述第二通道之一中的齿，所述齿定位成在所述至少一个电缆从所述第一方向转换到所述第二通道之前在所述多条电缆之间形成空间 方向。

公开(公告)号：US20050126808A1

公开(公告)日：2005-06-16

申请号：US10732975

申请日：2003-12-11

申请人： Philip Tousignant ,  Denis Foley ,  Robert Mondor

发明人： Philip Tousignant ,  Denis Foley ,  Robert Mondor

IPC分类号： H02G3/04 ,  H02G3/32

CPC分类号： H02G3/0437 ,  H02G3/32

摘要： One disclosed system comprises a first channel for routing at least one of a plurality of cables in a first direction; a second channel for routing said at least one cable in a second direction; and a plurality of teeth spaced apart from one another and disposed in one of said first channel and said second channel, said teeth positioned to create spaces in-between said plurality of cables before said at least one cable transitions from said first direction to said second direction.

摘要翻译： 一个公开的系统包括用于沿第一方向路由多个电缆中的至少一个的第一通道; 用于沿第二方向路由所述至少一个电缆的第二通道; 以及多个彼此间隔开并设置在所述第一通道和所述第二通道之一中的齿，所述齿定位成在所述至少一个电缆从所述第一方向转换到所述第二通道之前在所述多条电缆之间形成空间 方向。

公开(公告)号：US08397079B2

公开(公告)日：2013-03-12

申请号：US12133185

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G01R31/318536 ,  G01R31/318541

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 ROM或PROM中的秘密是安全的。 用于保护IC上的信息的一个实施例包括接收ROM读取命令，响应于接收到ROM读取命令将数据从多个ROM地址位置写入加密逻辑，并将加密逻辑的加密逻辑输出写入测试 控制逻辑，加密逻辑输出表示来自多个ROM地址位置的数据。 将数据从多个ROM地址位置写入加密逻辑还可以包括响应于ROM读命令将来自多个ROM地址位置的数据写入多输入移位寄存器（MISR），以及将MISR输出写入 测试控制逻辑，MISR输出表示来自多个ROM地址位置的数据。

公开(公告)号：US08051312B2

公开(公告)日：2011-11-01

申请号：US12123731

申请日：2008-05-20

申请人： Denis Foley

发明人： Denis Foley

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

摘要翻译： 集成电路包括能量控制器，其基于集成电路的期望目标频率值生成用于集成电路的电源电压电平。 能量控制器基于电源电压电平来配置可编程硬件过程传感器，使得可编程硬件过程传感器能够在以电源电压电平操作时模拟与集成电路相关联的预定关键路径的电特性。 通过在一段时间内监视可编程硬件过程传感器的频率，能量控制器可以将监控的频率与预期值进行比较，并确定电源电压电平是否可以被调整，还是应该保持。

公开(公告)号：US20100017893A1

公开(公告)日：2010-01-21

申请号：US12176580

申请日：2008-07-21

申请人： Denis Foley ,  Aris Balatsos

发明人： Denis Foley ,  Aris Balatsos

IPC分类号： G06F1/26

CPC分类号： G06F21/74

摘要： A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed.

摘要翻译： 系统包括处理装置，至少一个数据处理模块和安全控制模块。 安全控制模块可操作地连接到处理设备和数据处理模块。 安全控制模块可操作以控制与至少一个数据处理模块相关联的受保护寄存器的访问。 因此，安全控制模块作为防火墙或过滤器操作以允许或拒绝对受保护的寄存器的访问。 因此，安全性不知情的数据处理模块在中央位置被保护在系统中，而不需要仅使用安全感知数据处理模块。 还公开了一种用于保护数据处理模块的方法，包括安全性不知道的数据处理模块。

公开(公告)号：US06418176B1

公开(公告)日：2002-07-09

申请号：US09118527

申请日：1998-07-17

申请人： Steven Ho ,  Denis Foley

发明人： Steven Ho ,  Denis Foley

IPC分类号： H04L700

CPC分类号： H04L25/05 ,  H04L7/0008 ,  H04L7/005 ,  H04L7/02

摘要： A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.

摘要翻译： 技术提供来自信息信号的数据。 该技术涉及与转发的时钟信号同步地在转发的时钟设备中接收信息信号。 该技术还涉及恢复与恢复时钟信号同步的包含在信息信号内的数据，使得当恢复时钟信号对于转发的时钟设备具有最佳速率时，（i）特定周期等待时间恢复数据;以及（ii） 当恢复时钟信号具有次最佳速率时，不同的周期延迟。 特定的周期延迟可以包括比不同周期等待时间更多的周期。 因此，当恢复时钟信号具有次最佳速率时，时间延迟可能更短。