公开(公告)号：US08051345B2

公开(公告)日：2011-11-01

申请号：US12133173

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G11C7/24 ,  G11C29/12 ,  G11C29/14 ,  G11C2029/3202

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 确保存储在存储在ROM和/或PROM中的寄存器或锁存器，RAM和/或永久机密中的临时秘密。 用于保护IC上的信息的一个实施例包括响应于进入测试操作模式并在接收到测试模式命令之前进入测试模式并重置每个寄存器。 集成电路实施例包括测试控制逻辑，其可操作以将集成电路配置为测试模式并且在测试模式期间控制集成电路，一组寄存器以及耦合到测试控制逻辑的功能复位控制器 一组寄存器，用于从测试控制逻辑接收复位命令，并响应于进入测试模式的命令向该组寄存器提供复位命令。

公开(公告)号：US20090307502A1

公开(公告)日：2009-12-10

申请号：US12133185

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： H04L9/06

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G01R31/318536 ,  G01R31/318541

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 ROM或PROM中的秘密是安全的。 用于保护IC上的信息的一个实施例包括接收ROM读取命令，响应于接收到ROM读取命令将数据从多个ROM地址位置写入加密逻辑，并将加密逻辑的加密逻辑输出写入测试 控制逻辑，加密逻辑输出表示来自多个ROM地址位置的数据。 将数据从多个ROM地址位置写入加密逻辑还可以包括响应于ROM读命令将来自多个ROM地址位置的数据写入多输入移位寄存器（MISR），以及将MISR输出写入 测试控制逻辑，MISR输出表示来自多个ROM地址位置的数据。

公开(公告)号：US5625805A

公开(公告)日：1997-04-29

申请号：US269223

申请日：1994-06-30

申请人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

发明人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.

摘要翻译： 描述了同步计算机系统。 该系统是具有总线系统时钟和每个处理器的处理器时钟的多处理器系统。 该系统包括同步计算机系统总线和耦合到同步总线的多个电路模块，其中至少两个模块具有至少一个处理器，处理器模块具有至少一个处理器，其与另一个处理器异步运行 处理器，而处理器模块与系统总线同步。 该系统还包括用于提供对应的多个时钟信号的时钟发生器装置和耦合在所述时钟发生装置和所述多个模块之间的多个导体。 每个所述导体具有基本上相同的电路径长度的电路径，其中每个所述模块还包括耦合到所述导体中的相应一个导体并设置在所述模块上的装置，用于调节和调整所述模块上的时钟信号之间的偏差 。

公开(公告)号：US5559987A

公开(公告)日：1996-09-24

申请号：US268409

申请日：1994-06-30

申请人： Denis Foley ,  Maurice B. Steinman ,  Stephen R. VanDoren

发明人： Denis Foley ,  Maurice B. Steinman ,  Stephen R. VanDoren

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.

摘要翻译： 用于更新重复标签缓存状态信息的计算机系统中的方法和装置。 本发明在具有耦合到根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块的计算机系统中操作。 用于修改处理器的重复标签状态信息条目的处理器命令和地址由处理器提供给其到系统总线的地址接口。 系统总线命令和地址信息被接收并存储在地址接口的接口管道中。 确定接口管道中的系统总线命令和地址是否有效。 如果接口流水线中没有有效的系统总线命令和地址，则不会确定处理器命令和地址是否与系统总线命令和地址冲突，从而更新重复标签状态信息。

公开(公告)号：US20090288160A1

公开(公告)日：2009-11-19

申请号：US12122484

申请日：2008-05-16

申请人： James Lyall Esliger ,  Denis Foley

发明人： James Lyall Esliger ,  Denis Foley

IPC分类号： H04L9/32

CPC分类号： G06F21/572 ,  G06F21/575

摘要： An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

摘要翻译： 集成电路（100）可以经由调试访问端口（105）接收引导加载程序代码（114），其中启动逻辑可操作以在可编程处理器（103）的复位（123）从调试访问 端口（105），命令和来自调试访问端口的可编程处理器，同时仍然允许复位（123）命令，同时允许对存储器（112）的写访问以接收写入存储器的引导加载程序代码映像（114） 112）。 引导逻辑还从调试访问端口阻止对存储器子系统（109）的命令，并且在允许写入引导加载程序代码映像（114）之后，关闭对存储器（112）的写访问。 启动逻辑通过执行安全检查来验证引导加载程序代码映像（114），并且如果它有效则跳转到引导加载程序代码映像（114），从而允许其在可编程处理器（103）上运行。 引导逻辑可以是逻辑电路，软件或其组合。

公开(公告)号：US20090287895A1

公开(公告)日：2009-11-19

申请号：US12121573

申请日：2008-05-15

申请人： Denis Foley ,  Aris Balatsos

发明人： Denis Foley ,  Aris Balatsos

IPC分类号： G06F12/14 ,  G06F13/28

CPC分类号： G06F12/1433 ,  G06F21/79 ,  G06F21/85

摘要： A secure memory access system includes a memory control module, at least one direct memory access module, and a plurality of input/output interface modules. The direct memory access module is operative to transfer information between all of the input/output interface modules and the memory control module in response to transfer configuration information.

摘要翻译： 安全存储器访问系统包括存储器控制模块，至少一个直接存储器访问模块和多个输入/输出接口模块。 直接存储器访问模块可操作以响应于传送配置信息在所有输入/输出接口模块和存储器控制模块之间传送信息。

公开(公告)号：US06360285B1

公开(公告)日：2002-03-19

申请号：US08269234

申请日：1994-06-30

申请人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

发明人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

IPC分类号： G06F1202

CPC分类号： G06F13/16

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

摘要翻译： 根据本发明，一种装置包括具有存储体可用信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。 每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。 此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。 此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制 。 通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。 这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

公开(公告)号：US20090307411A1

公开(公告)日：2009-12-10

申请号：US12133173

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F1/12

CPC分类号： G01R31/318555 ,  G11C7/24 ,  G11C29/12 ,  G11C29/14 ,  G11C2029/3202

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 确保存储在存储在ROM和/或PROM中的寄存器或锁存器，RAM和/或永久机密中的临时秘密。 用于保护IC上的信息的一个实施例包括响应于进入测试操作模式并在接收到测试模式命令之前进入测试模式并重置每个寄存器。 集成电路实施例包括测试控制逻辑，其可操作以将集成电路配置为测试模式并且在测试模式期间控制集成电路，一组寄存器以及耦合到测试控制逻辑的功能复位控制器 一组寄存器，用于从测试控制逻辑接收复位命令，并响应于进入测试模式的命令向该组寄存器提供复位命令。

公开(公告)号：US20090289615A1

公开(公告)日：2009-11-26

申请号：US12123731

申请日：2008-05-20

申请人： Denis Foley

发明人： Denis Foley

IPC分类号： G05B24/02

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

摘要翻译： 集成电路包括能量控制器，其基于集成电路的期望目标频率值生成用于集成电路的电源电压电平。 能量控制器基于电源电压电平来配置可编程硬件过程传感器，使得可编程硬件过程传感器能够在以电源电压电平操作时模拟与集成电路相关联的预定关键路径的电特性。 通过在一段时间内监视可编程硬件过程传感器的频率，能量控制器可以将监控的频率与预期值进行比较，并确定电源电压电平是否可以被调整，还是应该保持。

公开(公告)号：US07345239B2

公开(公告)日：2008-03-18

申请号：US10732975

申请日：2003-12-11

申请人： Philip Tousignant ,  Denis Foley ,  Robert M. Mondor

发明人： Philip Tousignant ,  Denis Foley ,  Robert M. Mondor

IPC分类号： H02G3/04

CPC分类号： H02G3/0437 ,  H02G3/32

摘要： One disclosed system comprises a first channel for routing at least one of a plurality of cables in a first direction; a second channel for routing said at least one cable in a second direction; and a plurality of teeth spaced apart from one another and disposed in one of said first channel and said second channel, said teeth positioned to create spaces in-between said plurality of cables before said at least one cable transitions from said first direction to said second direction.

摘要翻译： 一个公开的系统包括用于沿第一方向路由多个电缆中的至少一个的第一通道; 用于沿第二方向布置所述至少一个电缆的第二通道; 以及多个彼此间隔开并设置在所述第一通道和所述第二通道之一中的齿，所述齿定位成在所述至少一个电缆从所述第一方向转换到所述第二通道之前在所述多条电缆之间形成空间 方向。