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    Partitioning of radio-frequency apparatus
    11.
    发明授权
    Partitioning of radio-frequency apparatus 有权
    射频设备分区

    公开(公告)号：US07242912B2

    公开(公告)日：2007-07-10

    申请号：US10631166

    申请日：2003-07-31

    Applicant: James Maligeorgos ,  Augusto M. Marques ,  Lysander Lim ,  G. Tyson Tuttle ,  Aslamali A. Rafi ,  Tod Paulus ,  Gregory T. Uehara ,  Jeffrey W. Scott ,  Richard T. Behrens ,  Donald A. Kerth ,  G. Diwakar Vishakhadatta ,  Vishnu S. Srinivasan ,  Caiyi Wang

    Inventor： James Maligeorgos ,  Augusto M. Marques ,  Lysander Lim ,  G. Tyson Tuttle ,  Aslamali A. Rafi ,  Tod Paulus ,  Gregory T. Uehara ,  Jeffrey W. Scott ,  Richard T. Behrens ,  Donald A. Kerth ,  G. Diwakar Vishakhadatta ,  Vishnu S. Srinivasan ,  Caiyi Wang

    IPC: H04B1/40

    CPC classification number: H04B1/0003 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/28 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064

    Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

    Abstract translation: 包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。 频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。 频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。 可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。 自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。 数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

    Phase locked loop circuitry for synthesizing high-frequency signals and associated method
    13.
    发明授权
    Phase locked loop circuitry for synthesizing high-frequency signals and associated method 有权
    用于合成高频信号和相关方法的锁相环电路

    公开(公告)号：US06549765B2

    公开(公告)日：2003-04-15

    申请号：US09933530

    申请日：2001-08-20

    Applicant: David R. Welland ,  Caiyi Wang

    Inventor： David R. Welland ,  Caiyi Wang

    IPC: H04B126

    CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

    Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

    METHOD AND APPARATUS FOR REDUCING INTERFERENCE
    14.
    发明申请
    METHOD AND APPARATUS FOR REDUCING INTERFERENCE 有权
    减少干扰的方法和装置

    公开(公告)号：US20100102877A1

    公开(公告)日：2010-04-29

    申请号：US12650546

    申请日：2009-12-31

    Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

    IPC: H03B1/04

    CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

    Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

    Selectable threshold multimode gain control apparatus and method for setting mutually continuous analog, digital, and shutter gain levels
    16.
    发明授权
    Selectable threshold multimode gain control apparatus and method for setting mutually continuous analog, digital, and shutter gain levels 有权
    可选择的阈值多模增益控制装置和方法，用于设置相互连续的模拟，数字和快门增益级别

    公开(公告)号：US07589766B2

    公开(公告)日：2009-09-15

    申请号：US10659472

    申请日：2003-09-10

    Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

    Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

    IPC: H04N5/235 ,  H04N5/238

    CPC classification number: H04N5/2352 ,  H04N5/243

    Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

    Abstract translation: 一种用于电荷耦合器件（CCD）或CMOS成像系统的可选阈值多模增益控制装置和方法，包括一自动增益控制（AGC）电路，其连续地控制所述CCD系统中的增益以产生相互连续的组合目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

    PARTITIONING OF RADIO-FREQUENCY APPARATUS
    17.
    发明申请
    PARTITIONING OF RADIO-FREQUENCY APPARATUS 有权
    无线电频率设备的分配

    公开(公告)号：US20070054629A1

    公开(公告)日：2007-03-08

    申请号：US10730404

    申请日：2003-12-08

    Applicant: James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

    Inventor： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

    IPC: H04B1/38

    CPC classification number: H04B1/30 ,  H03J2200/10 ,  H04L27/0002

    Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

    Abstract translation: 包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。 频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。 频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。 可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。 自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。 数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

    Controlled oscillator circuitry for synthesizing high-frequency signals and associated method
    18.
    发明授权
    Controlled oscillator circuitry for synthesizing high-frequency signals and associated method 有权
    用于合成高频信号的控制振荡器电路及相关方法

    公开(公告)号：US06965761B2

    公开(公告)日：2005-11-15

    申请号：US10358563

    申请日：2003-02-05

    Applicant: David R. Welland ,  Caiyi Wang

    Inventor： David R. Welland ,  Caiyi Wang

    IPC: H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/193 ,  H03L7/199 ,  H03L7/23 ,  H04B1/06 ,  H04B1/40 ,  H04B7/00 ,  H03B5/24

    CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

    Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

    Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications
    19.
    发明授权
    Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications 有权

    公开(公告)号：US06741846B1

    公开(公告)日：2004-05-25

    申请号：US09708339

    申请日：2000-11-08

    Applicant: David R. Welland ,  Caiyi Wang

    Inventor： David R. Welland ,  Caiyi Wang

    IPC: H04B700

    CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23

    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

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