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18 条记录 (耗时 0.027 秒)

    Transistor having a protruded drain
    11.
    发明授权
    Transistor having a protruded drain 有权
    具有突出漏极的晶体管

    公开(公告)号：US07419880B2

    公开(公告)日：2008-09-02

    申请号：US11705355

    申请日：2007-02-12

    申请人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

    发明人： Tae-Jung Lee ,  Soo-Cheol Lee ,  Dong-Ryul Chang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0882 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/7835

    摘要： A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

    摘要翻译： 场效应晶体管包括形成在限定在衬底上的有源区的沟道区中的栅极。 源极形成在相邻地设置在栅极的第一侧面的有源区的第一表面部分处。 在有源区域的与栅极相对的第一表面部分的第二表面部分处形成漏极。 漏极具有从基板的表面部突出的突出部。

    System-on-chip including DRAM and analog device for improving DRAM capacitance and method for fabricating the same
    13.
    发明授权
    System-on-chip including DRAM and analog device for improving DRAM capacitance and method for fabricating the same 有权
    片上系统，包括用于改善DRAM电容的DRAM和模拟装置及其制造方法

    公开(公告)号：US07075136B2

    公开(公告)日：2006-07-11

    申请号：US10922439

    申请日：2004-08-19

    申请人： Dong-Ryul Chang

    发明人： Dong-Ryul Chang

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L28/75 ,  H01L28/91

    摘要： Provided is an invention related to a SOC containing a DRAM and an analog device for increasing a capacitance of a capacitor in SOC and a method of fabricating the SOC. Two conductive layers are used for lower electrode in a capacitor for unit cells of the DRAM, and the whole surface of the upper electrode is capped with a second dielectric layer to maximally increase in the contact surface between the dielectric layer and the upper and lower electrodes.

    摘要翻译： 提供了涉及包含DRAM的SOC和用于增加SOC中的电容器的电容的模拟装置的发明以及制造SOC的方法。 在DRAM的单元电池的电容器中使用两个导电层，并且上部电极的整个表面被第二介电层覆盖，以使电介质层和上下电极之间的接触表面最大程度地增加 。

    System-on-chip including DRAM & analog device for improving DRAM capacitance and method for fabricating the same
    14.
    发明申请
    System-on-chip including DRAM & analog device for improving DRAM capacitance and method for fabricating the same 有权
    片上系统，包括用于改善DRAM电容的DRAM和模拟装置及其制造方法

    公开(公告)号：US20050048719A1

    公开(公告)日：2005-03-03

    申请号：US10922439

    申请日：2004-08-19

    申请人： Dong-Ryul Chang

    发明人： Dong-Ryul Chang

    IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/105

    CPC分类号： H01L27/105 ,  H01L28/75 ,  H01L28/91

    摘要： Provided is an invention related to a SOC containing a DRAM and an analog device for increasing a capacitance of a capacitor in SOC and a method of fabricating the SOC. Two conductive layers are used for lower electrode in a capacitor for unit cells of the DRAM, and the whole surface of the upper electrode is capped with a second dielectric layer to maximally increase in the contact surface between the dielectric layer and the upper and lower electrodes.

    摘要翻译： 提供了涉及包含DRAM的SOC和用于增加SOC中的电容器的电容的模拟装置的发明以及制造SOC的方法。 在DRAM的单元电池的电容器中使用两个导电层，并且上部电极的整个表面被第二介电层覆盖，以使电介质层和上下电极之间的接触表面最大程度地增加 。

    Nonvolatile memory device and method of manufacturing same
    15.
    发明授权
    Nonvolatile memory device and method of manufacturing same 有权
    非易失存储器件及其制造方法

    公开(公告)号：US08866211B2

    公开(公告)日：2014-10-21

    申请号：US13076910

    申请日：2011-03-31

    申请人： Dong-Ryul Chang ,  Myoung-Kyu Park

    发明人： Dong-Ryul Chang ,  Myoung-Kyu Park

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/11519

    摘要： A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.

    摘要翻译： 包括其中多个单元电池至少沿一个方向排列的单元阵列区域的非易失性存储器件包括形成在各个单元电池中的多个存储晶体管。 每个存储晶体管包括其中层叠有隧道绝缘层，浮栅，栅极间绝缘层和控制栅极的栅极图案，以及布置在栅极图案的相对侧上的第一和第二接合区域，其中栅极 图案沿单位单元在一个方向上分离。 非易失性存储器件还包括在一个方向上延伸并且被布置在与控制栅极和多个第一触点重叠的位置的第一导电互连，其中至少一个布置用于每个控制栅极连接 控制门和第一导电互连。

    Semiconductor integrated circuit device and method of fabricating the same
    16.
    发明申请
    Semiconductor integrated circuit device and method of fabricating the same 审中-公开
    半导体集成电路器件及其制造方法

    公开(公告)号：US20090278208A1

    公开(公告)日：2009-11-12

    申请号：US12457823

    申请日：2009-06-23

    申请人： Dong-Ryul Chang

    发明人： Dong-Ryul Chang

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42368

    摘要： A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern.

    摘要翻译： 提供了具有更高集成密度的半导体集成电路器件及其制造方法。 半导体集成电路器件可以包括限定有源区的半导体衬底中的沟槽隔离区域和用于更高电压并形成在半导体衬底的有源区上的栅极图案。 可以在栅极图案的边缘上和周围的半导体衬底中形成沟槽绝缘层，以便能够减轻来自栅极图案的电场。 每个沟槽绝缘层的深度可以根据工作电压来定义。 源极和漏极区域包围沟槽绝缘层，并且可以形成在栅极图案的两侧上的半导体衬底中。 因此，半导体集成电路器件可以具有更高的集成密度并且可以缓解来自栅极图案的电场。