公开(公告)号：US20100093166A1

公开(公告)日：2010-04-15

申请号：US12587857

申请日：2009-10-14

申请人： Tae-Gyun Kim ,  Dong-Suk Shin

发明人： Tae-Gyun Kim ,  Dong-Suk Shin

IPC分类号： H01L21/283 ,  H01L21/31

CPC分类号： H01L21/76224 ,  H01L21/02315 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3115 ,  H01L29/42368 ,  H01L29/78

摘要： In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced.

摘要翻译： 在制造半导体器件的方法中，在衬底的有源区上形成掩模图案。 去除衬底的暴露部分以在衬底中形成沟槽。 在沟槽的底部和侧壁和掩模图案上形成初步的第一绝缘层。 使用含氟等离子体对预备的第一绝缘层进行等离子体处理，以形成包含氟的第一绝缘层。 在第一绝缘层上形成第二绝缘层以填充沟槽。 可以选择性地增加与沟槽的上边缘相邻的栅极绝缘层的厚度，并且可以减少漏电流的产生。

公开(公告)号：US20090004800A1

公开(公告)日：2009-01-01

申请号：US12213502

申请日：2008-06-20

申请人： Dong Suk Shin ,  Joo-Won Lee ,  Tae-Gyun Kim

发明人： Dong Suk Shin ,  Joo-Won Lee ,  Tae-Gyun Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/263 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/7833

摘要： In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.

摘要翻译： 在制造半导体器件的方法中，可以在衬底上形成导电层图案。 可以在衬底上形成氧化物层以覆盖导电层图案。 可以通过处理氧化物层以增加杂质扩散所需的能量来形成扩散阻挡层。 可以通过在扩散阻挡层中将杂质注入到导电层图案和邻近导电层图案的衬底的一部分而在衬底上形成杂质区。 可以防止或减少导电层图案和杂质区域中的杂质的扩散，因此，半导体器件可以具有改进的性能。

公开(公告)号：US20080166854A1

公开(公告)日：2008-07-10

申请号：US12052257

申请日：2008-03-20

申请人： Dong-Suk Shin ,  Tae-Gyun Kim

发明人： Dong-Suk Shin ,  Tae-Gyun Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76232

摘要： Trench isolation methods include forming a first trench and a second trench in a semiconductor substrate. The second trench has a larger width than the first trench. A tower isolation layer is formed on the semiconductor substrate using a first high density plasma deposition process. The lower isolation layer has a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench. The second thickness is greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The second high density plasma deposition process includes an H2 treatment process.

摘要翻译： 沟槽隔离方法包括在半导体衬底中形成第一沟槽和第二沟槽。 第二沟槽具有比第一沟槽更大的宽度。 使用第一高密度等离子体沉积工艺在半导体衬底上形成塔隔离层。 下隔离层在第​​一沟槽的上侧壁上具有第一厚度，在第二沟槽的上侧壁上具有第二厚度。 第二厚度大于第一厚度。 使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。 第二高密度等离子体沉积工艺包括H 2 N 2处理工艺。

公开(公告)号：US20090132730A1

公开(公告)日：2009-05-21

申请号：US12300763

申请日：2007-05-15

申请人： Kyung-Beom Kim ,  Young-Hwan Kim ,  Tae-Gyun Kim ,  Min-sick Park ,  Jae-Han Lee ,  Jang Gwang-Sig ,  Sang-Hyun Han

发明人： Kyung-Beom Kim ,  Young-Hwan Kim ,  Tae-Gyun Kim ,  Min-sick Park ,  Jae-Han Lee ,  Jang Gwang-Sig ,  Sang-Hyun Han

IPC分类号： G06F3/00

CPC分类号： G06F1/266

摘要： The present invention relates to an apparatus and method for controlling power to a Universal Serial Bus (USB) device. The present invention provides an apparatus for controlling power to a USB device, the USB device being used to connect a Personal Computer (PC) with a peripheral device, the power control apparatus including a plug-in port for connecting the peripheral device with the PC, a state detector for detecting whether the peripheral device is in a preparation completion state, a power supply unit for supplying power to the USB device, and a power control unit for controlling the power supply unit so that power is supplied to the USB device if it is determined that the peripheral device is in a plugged-in state, and if it is determined that the peripheral device is in a preparation completion state by the state detector. Accordingly, the present invention performs the supply of power only when the peripheral device is plugged into the USB device and its internal application program is in a preparation completion state, so that it can prevent power from being unnecessarily consumed.

摘要翻译： 本发明涉及一种用于控制通用串行总线（USB）设备的电源的设备和方法。 本发明提供了一种用于控制USB设备的电力的装置，所述USB设备用于将个人计算机（PC）与外围设备连接，所述电源控制设备包括用于将外围设备与PC连接的插入端口 ，用于检测外围设备是否处于准备完成状态的状态检测器，用于向USB设备供电的电源单元以及用于控制电源单元的电源控制单元，以便向USB设备供电如果 确定外围设备处于插入状态，并且如果通过状态检测器确定外围设备处于准备完成状态。 因此，本发明仅在外围设备插入USB设备并且其内部应用程序处于准备完成状态时才进行供电，从而可以防止功率被不必要地消耗。

公开(公告)号：US20060224789A1

公开(公告)日：2006-10-05

申请号：US11320874

申请日：2005-12-30

申请人： Hyun-Duk Cho ,  Young-Joon Choi ,  Tae-Gyun Kim

发明人： Hyun-Duk Cho ,  Young-Joon Choi ,  Tae-Gyun Kim

IPC分类号： G06F5/00

CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/22

摘要： A memory may include first and second buffer memories and a memory core. The memory core may include memory blocks each having a plurality of pages and a page buffer for reading data from a selected memory block. A control logic may control the first and second buffer memories and the memory core. The control logic may have a register for storing address and command information of the memory core. The control logic may control the memory core so that data read periods for pages of the selected memory block are carried out according to the stored address and command information. The control logic may control the first and second buffer memories and the memory core so that data in the page buffer may be transferred to the first and/or second buffer memories during the data read periods. The control logic may deactivate an interrupt signal when data in the page buffer is transferred to the first and/or second buffer memory and may activate the interrupt signal when data in the first and/or second buffer memory is transferred to an external storage.

摘要翻译： 存储器可以包括第一和第二缓冲存储器和存储器核。 存储器核心可以包括每个具有多个页面的存储器块和用于从所选择的存储器块读取数据的页面缓冲器。 控制逻辑可以控制第一和第二缓冲存储器和存储器核。 控制逻辑可以具有用于存储存储器核心的地址和命令信息的寄存器。 控制逻辑可以控制存储器核，使得根据存储的地址和命令信息执行所选存储器块的页面的数据读取周期。 控制逻辑可以控制第一和第二缓冲存储器和存储器核，使得在数据读取周期期间页缓冲器中的数据可以被传送到第一和/或第二缓冲存储器。 当页面缓冲器中的数据被传送到第一和/或第二缓冲存储器时，控制逻辑可以去激活中断信号，并且当第一和/或第二缓冲存储器中的数据被传送到外部存储器时可以激活中断信号。

公开(公告)号：US08368852B2

公开(公告)日：2013-02-05

申请号：US12838758

申请日：2010-07-19

申请人： Chang-Hun Kwak ,  Jae-Jun Yu ,  Tae-Gyun Kim ,  Jang-Sub Kim

发明人： Chang-Hun Kwak ,  Jae-Jun Yu ,  Tae-Gyun Kim ,  Jang-Sub Kim

IPC分类号： G02F1/1333

CPC分类号： G02B5/201 ,  G02B5/223 ,  G02F1/133512 ,  G02F1/133516 ,  H01L29/786

摘要： A display panel includes; a substrate, and a light blocking structure surrounding an ink filling region on the substrate, the light blocking structure including; a first layer pattern having an ink affinity characteristic disposed on the substrate, and a second layer pattern positioned on the first layer pattern and including an organic material having a light blocking characteristic.

公开(公告)号：US07581070B2

公开(公告)日：2009-08-25

申请号：US11228192

申请日：2005-09-19

申请人： Hyun-Duk Cho ,  Tae-Gyun Kim

发明人： Hyun-Duk Cho ,  Tae-Gyun Kim

IPC分类号： G06F12/00 ,  G06F15/177

CPC分类号： G06F13/1673 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/44573

摘要： A multi-chip package device includes first and second memory chips configured to share addresses and control signals. The first and second memory chips each include main memory, buffer memory, an option terminal for receiving an option voltage, an access signal generation block, and a controller. The main memory of the first memory chip stores boot code. The buffer memory of the first memory chip includes boot memory. The option voltages of the first and second memory chips have different voltage levels. The access signal generation block generates a buffer access signal that undergoes a one-way transition in response to the boot code address. The one-way transition of the buffer access signal of the first memory chip is a transition to activation, and the one-way transition of the buffer access signal of the second memory chip is a transition to inactivation.

摘要翻译： 多芯片封装器件包括被配置为共享地址和控制信号的第一和第二存储器芯片。 第一和第二存储器芯片各自包括主存储器，缓冲存储器，用于接收选项电压的选项端子，访问信号生成块和控制器。 第一个存储器芯片的主存储器存储引导代码。 第一存储器芯片的缓冲存储器包括引导存储器。 第一和第二存储器芯片的选项电压具有不同的电压电平。 访问信号生成块生成响应于引导代码地址经历单向转换的缓冲器访问信号。 第一存储器芯片的缓冲器访问信号的单向转换是转换到激活，并且第二存储器芯片的缓冲器访问信号的单向转换是转换到失活。

公开(公告)号：US07085167B2

公开(公告)日：2006-08-01

申请号：US11009125

申请日：2004-12-10

申请人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim

发明人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim

IPC分类号： G11C6/04 ,  G11C11/34

CPC分类号： G11C16/225

摘要： Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

公开(公告)号：US07571276B2

公开(公告)日：2009-08-04

申请号：US11542140

申请日：2006-10-04

申请人： Hyun-Duk Cho ,  Tae-Gyun Kim

发明人： Hyun-Duk Cho ,  Tae-Gyun Kim

IPC分类号： G06F12/00

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host. The method comprising; sensing data stored in one page of the memory cell array in the page buffer, transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations, and reading the transferred data from the data RAM in response to the host clock signal, wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

摘要翻译： 公开了一种在NAND / RAM半导体存储器件中执行读取操作的方法。 半导体存储器件包括具有存储单元阵列和页缓冲器的NAND闪速存储器件，以及响应于从主机接收的时钟信号而输出数据的数据RAM。 该方法包括： 感测存储在页面缓冲器中的存储单元阵列的一页中的数据，经由相应数量的传送操作将感测数据从页缓冲器传送到数据RAM，并响应于从数据RAM读取传送的数据 对于主机时钟信号，其中在所述多个传送时间段中的任何一个期间，所传输的数据的读出操作开始。

公开(公告)号：US07004140B2

公开(公告)日：2006-02-28

申请号：US10749222

申请日：2003-12-30

申请人： Tae-Gyun Kim

发明人： Tae-Gyun Kim

IPC分类号： F02B3/00

CPC分类号： F02B23/0627 ,  F02B23/0672 ,  F02F3/24 ,  F02F3/26 ,  Y02T10/125

摘要： A piston structure of an engine generates an automatic flow of gas through a hole penetrating from a bowl of the piston toward a lateral side of the piston. The structure provides a reinforcement of the compression and swirling movement in the combustion chamber of an engine, improvement of the mixture function of the fuel and air, reduction of the blowby leaking into the crankcase through the clearance between the cylinder wall and the piston, and prevention of the wear and tear of the cylinder liner and piston by eliminating wet fuel formed on the cylinder wall.

摘要翻译： 发动机的活塞结构通过从活塞碗穿过活塞的侧面的孔产生气体的自动流动。 该结构提供了在发动机的燃烧室中的压缩和旋转运动的加强，燃料和空气的混合功能的改善，通过气缸壁和活塞之间的间隙减少到曲轴箱的泄漏，以及 通过消除汽缸壁上形成的湿燃料来防止气缸套和活塞的磨损。