公开(公告)号：US11798646B2

公开(公告)日：2023-10-24

申请号：US17512392

申请日：2021-10-27

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Jason Janesky ,  Han Kyu Lee ,  Hamid Almasi ,  Pedro Sanchez ,  Cristian P. Masgras ,  Iftekhar Rahman ,  Sumio Ikegawa ,  Sanjeev Aggarwal ,  Dimitri Houssameddine ,  Frederick Charles Neumeyer

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401 ,  G11C2029/0407 ,  G11C2029/1202

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US11488647B2

公开(公告)日：2022-11-01

申请号：US17255915

申请日：2019-06-27

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Frederick Mancoff ,  Jason Janesky ,  Kevin Conley ,  Lu Hui ,  Sumio Ikegawa

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

公开(公告)号：US11264564B2

公开(公告)日：2022-03-01

申请号：US16783740

申请日：2020-02-06

Applicant: Everspin Technologies, Inc.

Inventor： Sumio Ikegawa ,  Hamid Almasi ,  Shimon ,  Kerry Nagel ,  Han Kyu Lee

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.

公开(公告)号：US20190131519A1

公开(公告)日：2019-05-02

申请号：US16179112

申请日：2018-11-02

Applicant: Everspin Technologies Inc.

Inventor： Sumio Ikegawa ,  Jon Slaughter ,  Renu Whig

IPC: H01L43/10 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01F41/32 ,  G11C11/16

Abstract: A magnetoresistive stack includes a seed region formed above a base region, a fixed magnetic region formed above the seed region and an intermediate region positioned between the fixed magnetic region and a free magnetic region. The base region may be formed of a material having a lower standard free energy of oxidation than iron.