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    DESALINATION PLANT
    12.
    发明申请
    DESALINATION PLANT 有权
    脱盐设备

    公开(公告)号：US20130153398A1

    公开(公告)日：2013-06-20

    申请号：US13808543

    申请日：2011-06-24

    申请人： Hui Tong Chua ,  Xiaolin Wang ,  Klaus Regenauer-Lieb

    发明人： Hui Tong Chua ,  Xiaolin Wang ,  Klaus Regenauer-Lieb

    IPC分类号： C02F1/04

    CPC分类号： C02F1/043 ,  B01D3/143 ,  C02F1/048 ,  Y02A20/128

    摘要： There is provided an apparatus 2 for desalinating non-potable water. The apparatus comprises a first vapour producing module 5 configured to receive a heated working fluid for producing vapour from a volume of non-potable water for driving at least one first distillation module 10 for producing condensate 12. The apparatus further comprises a second vapour producing module 14 configured to receive working fluid from the first vapour producing module 5 for producing additional vapour from a further volume of non-potable water 8′.

    摘要翻译： 提供了用于使非饮用水脱盐的装置2。 该设备包括第一蒸气产生模块5，其被配置为接收用于从一定体积的非饮用水产生蒸汽的加热的工作流体，用于驱动至少一个用于产生冷凝物12的第一蒸馏模块10.该设备还包括第二蒸气产生模块 14，其构造成从第一蒸气产生模块5接收工作流体，用于从另一体积的非饮用水8'产生额外的蒸汽。

    RECONFIGURABLE MICROPROCESSOR HARDWARE ARCHITECTURE
    13.
    发明申请
    RECONFIGURABLE MICROPROCESSOR HARDWARE ARCHITECTURE 审中-公开

    公开(公告)号：US20190056941A1

    公开(公告)日：2019-02-21

    申请号：US16168088

    申请日：2018-10-23

    申请人： Xiaolin Wang ,  Qian Wu

    发明人： Xiaolin Wang ,  Qian Wu

    IPC分类号： G06F9/30 ,  H04B1/00 ,  G06F17/50 ,  G06F9/455 ,  G06F15/78 ,  G06F15/76

    CPC分类号： G06F9/30181 ,  G06F9/455 ,  G06F15/76 ,  G06F15/7867 ,  G06F17/5054 ,  G06F2015/768 ,  H04B1/0003

    摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.

    RECONFIGURABLE MICROPROCESSOR HARDWARE ARCHITECTURE
    14.
    发明申请
    RECONFIGURABLE MICROPROCESSOR HARDWARE ARCHITECTURE 审中-公开

    公开(公告)号：US20180143834A1

    公开(公告)日：2018-05-24

    申请号：US15876696

    申请日：2018-01-22

    申请人： Xiaolin Wang ,  Qian Wu

    发明人： Xiaolin Wang ,  Qian Wu

    IPC分类号： G06F9/30 ,  H04B1/00 ,  G06F17/50 ,  G06F9/455 ,  G06F15/78 ,  G06F15/76

    CPC分类号： G06F9/30181 ,  G06F9/455 ,  G06F15/76 ,  G06F15/7867 ,  G06F17/5054 ,  G06F2015/768 ,  H04B1/0003

    摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

    Instruction set design, control and communication in programmable microprocessor cores and the like
    15.
    发明授权
    Instruction set design, control and communication in programmable microprocessor cores and the like 有权
    可编程微处理器内核中的指令集设计，控制和通信等

    公开(公告)号：US08181003B2

    公开(公告)日：2012-05-15

    申请号：US12156007

    申请日：2008-05-29

    申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

    发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

    摘要： Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

    摘要翻译： 公开了针对可编程微处理器的改进的指令集和核心设计，控制和通信，其涉及用新的分布式程序排序代替当前和现有技术处理器中的集中程序排序的策略，其中每个功能单元具有其自己的指令获取和解码块 ，并且每个功能单元具有其自己的用于程序存储的本地存储器; 并且其中响应于建立硬件单元的不同配置和切换互连的变化的应用指令序列，计算硬件执行单元和存储器单元被灵活地流水线化为具有不同顺序的可重新配置流水线级的可编程嵌入式处理器。

    PREPARATION METHOD OF (3S,4S)-3-HEXYL-4-((R)-2-HYDROXYTRIDECYL)-OXETAN-2-0NE AND THE PRODUCT OF THAT METHOD
    16.
    发明申请
    PREPARATION METHOD OF (3S,4S)-3-HEXYL-4-((R)-2-HYDROXYTRIDECYL)-OXETAN-2-0NE AND THE PRODUCT OF THAT METHOD 有权
    （3S，4S）-3-甲基-4 - （（R）-2-羟基吡啶基） - 异-2-烯的制备方法及其制法

    公开(公告)号：US20110046400A1

    公开(公告)日：2011-02-24

    申请号：US12990111

    申请日：2008-05-26

    申请人： Yong Qin ,  Xianglin Deng ,  Xuan Zhou ,  Guofeng Yu ,  Ke Wang ,  Hao Song ,  Xiaolin Wang ,  Shan Huang

    发明人： Yong Qin ,  Xianglin Deng ,  Xuan Zhou ,  Guofeng Yu ,  Ke Wang ,  Hao Song ,  Xiaolin Wang ,  Shan Huang

    IPC分类号： C07D305/12

    CPC分类号： C07D305/12 ,  C07D213/70

    摘要： The present invention relates to a method for the preparation of (3S,4S)-3-hexyl-4-((R)-2-hydroxytridecyl)-oxetan-2-one and a product of the method. The method includes the following steps: a) reducing a substance represented by formula (II) to obtain a substance represented by formula (III), and then oxidizing the substance represented by formula (III) to form a substance represented by formula (IV); b) acylating n-octanoic acid to obtain n-octanoyl chloride using thionyl dichloride, then condensing the obtained n-octanoyl chloride with 2-mercapto-pyridine under basic condition to form a substance represented by formula (V), and then converting the substance represented by formula (V) to a substance represented by formula (VI); c) reacting the substance obtained in the step a) with the substance obtained in the step b) under catalytic condition of Lewis acid to generate a substance represented by formula (VII), and then reacting with a Lewis acid. The meanings of the signs in these formulas are the same as those in the description.

    摘要翻译： 本发明涉及制备（3S，4S）-3-己基-4 - （（R）-2-羟基十三烷基）氧杂环丁烷-2-酮的方法和该方法的产物。 该方法包括以下步骤：a）还原由式（II）表示的物质以获得由式（III）表示的物质，然后氧化由式（III）表示的物质以形成由式（IV）表示的物质， ; b）用正辛酸酰化得到正辛酰氯，然后在碱性条件下将所得的正辛酰氯与2-巯基 - 吡啶缩合形成式（Ⅴ）表示的物质，然后转化成物质 由式（Ⅴ）代表由式（Ⅵ）表示的物质; c）在路易斯酸的催化条件下，使步骤a）中获得的物质与步骤b）中获得的物质反应，生成由式（Ⅶ）表示的物质，然后与路易斯酸反应。 这些公式中的符号的含义与描述中的符号的含义相同。

    Projection light
    18.
    外观设计
    Projection light 有权

    公开(公告)号：USD998226S1

    公开(公告)日：2023-09-05

    申请号：US29834726

    申请日：2022-04-13

    申请人： Xiaolin Wang

    设计人： Xiaolin Wang

    摘要： The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will b e provided by the Office upon request and payment of the necessary fee.
    FIG. 1 is a front elevational view of a projection light showing my new design;
    FIG. 2 is a rear elevational view thereof;
    FIG. 3 is a left side view thereof;
    FIG. 4 is a right side view thereof;
    FIG. 5 is a perspective view thereof;
    FIG. 6 is a second perspective view thereof;
    FIG. 7 is a third perspective view thereof; and,
    FIG. 8 is a fourth perspective view thereof.
    The part of the photograph shown in a coarser dot pattern within the broken-line perimeter, as well as the broken-line perimeter itself, illustrates a portion of the projection light that forms no part of the claimed design.

    METHOD AND SYSTEM FOR EXEMPLAR LEARNING FOR TEMPLATIZING DOCUMENTS ACROSS DATA SOURCES
    19.
    发明公开
    METHOD AND SYSTEM FOR EXEMPLAR LEARNING FOR TEMPLATIZING DOCUMENTS ACROSS DATA SOURCES 审中-公开

    公开(公告)号：US20230196007A1

    公开(公告)日：2023-06-22

    申请号：US18067086

    申请日：2022-12-16

    申请人： Xiaolin Wang

    发明人： Xiaolin Wang ,  Michael Rinehart

    IPC分类号： G06F40/186 ,  G06N5/022 ,  G06F40/205 ,  G06F40/194

    CPC分类号： G06F40/186 ,  G06N5/022 ,  G06F40/205 ,  G06F40/194

    摘要： A system and method for templatizing documents across data sources is disclosed. The system includes a scanner to scan a plurality of files to retrieve a plurality of textual content. The system includes a pre-processor module to refine an efficacy corresponding to the scanned plurality of files by using a classifier to identify textual content with a similar template. The system includes an extraction module to extract a plurality of common sequences and sub-sequences from the plurality of files. The system includes a ranking module to rank the plurality of common sequences and sub-sequences based on a score. The system includes a feature vector generating module to generate a feature vector from the plurality of common sequences and sub-sequences. The system includes a determining module to determine a threshold value for the classifier thereby developing the classifier automatically to search for positive files with similar templates in the organization.