利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.034 秒)

    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME
    12.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 有权
    具有用于嵌入式动态随机存取存储器（EDRAM）的集成四元组电容器的半导体结构及其形成方法

    公开(公告)号：US20120326274A1

    公开(公告)日：2012-12-27

    申请号：US13165615

    申请日：2011-06-21

    申请人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    发明人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/91

    摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.

    摘要翻译： 描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。 例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 金属板的四重布置设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽的侧壁和金属板的四重布置上。 顶部金属板层设置在第二介电层上并与第二介质层保形。

    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
    13.
    发明申请
    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application 审中-公开
    集成电路，含有1T-1C的嵌入式存储单元以及用于嵌入式存储器应用的1T-1C存储单元的制造方法

    公开(公告)号：US20100155801A1

    公开(公告)日：2010-06-24

    申请号：US12317507

    申请日：2008-12-22

    申请人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    发明人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    摘要翻译： 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）和至少部分地嵌入在半导体衬底内的电容器（130），使得电容器完全在导电层的下面。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以用作包括半导体衬底的1T-1C嵌入式存储单元，半导体衬底上的电绝缘堆叠（160），包括源极/漏极区域（142）的晶体管（140） ）和在半导体衬底上方的栅极区（141），延伸穿过电绝缘层并进入半导体衬底的沟槽（111），位于沟槽内的第一电绝缘层（131）和电容器 位于第一电绝缘层的沟槽内部。

    Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same
    15.
    发明授权
    Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same 有权
    具有用于嵌入式动态随机存取存储器（eDRAM）的集成四足壁电容器的半导体结构及其形成方法

    公开(公告)号：US08519510B2

    公开(公告)日：2013-08-27

    申请号：US13165615

    申请日：2011-06-21

    申请人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    发明人： Brian S. Doyle ,  Uday Shah ,  Satyarth Suri ,  Ramanan V. Chebiam

    IPC分类号： H01L29/92

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/91

    摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.

    摘要翻译： 描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。 例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 金属板的四重布置设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽的侧壁和金属板的四重布置上。 顶部金属板层设置在第二介电层上并与第二介质层保形。