公开(公告)号：US20130234290A1

公开(公告)日：2013-09-12

申请号：US13868273

申请日：2013-04-23

Applicant: Steven Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

Inventor： Steven Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract translation: 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

公开(公告)号：US20050148147A1

公开(公告)日：2005-07-07

申请号：US10750054

申请日：2003-12-30

Applicant: Steven Keating ,  Chris Auth

Inventor： Steven Keating ,  Chris Auth

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/165 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/165

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract translation: 描述通过在衬底内注入具有电中性元素的衬底来形成非晶态蚀刻停止层的方法。 在衬底内使用电气中性的元件如果它们扩散到衬底内的其它区域，则防止元件的电干扰。 非晶蚀刻停止层可用作制造晶体管或诸如悬臂的其它器件的硬掩模。

公开(公告)号：US20090035911A1

公开(公告)日：2009-02-05

申请号：US11830155

申请日：2007-07-30

Applicant: Willy Rachmady ,  Steven Keating ,  Bernhard Sell

Inventor： Willy Rachmady ,  Steven Keating ,  Bernhard Sell

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.

Abstract translation: 一种用于形成具有突变的超浅表面尖端区域的半导体器件的方法包括在晶体衬底上形成栅极堆叠，执行第一离子注入工艺以使位于邻近和相对侧两侧的衬底的第一对区域非晶化 所述栅堆叠在所述衬底上形成一对间隔物，所述衬底设置在所述栅堆叠的横向相对侧上，执行第二离子注入工艺以使位于所述栅叠层的横向相对侧上的所述衬底的第二对区域非晶化;以及 邻近所述间隔物，施加选择性湿法蚀刻化学物质以去除所述非晶化的第一和第二对区域并在所述栅极堆叠的横向相对侧上形成一对空腔，以及在所述一对空腔中沉积硅合金以形成源和 漏极区域和源极和漏极表面尖端区域。

公开(公告)号：US20080242102A1

公开(公告)日：2008-10-02

申请号：US11692349

申请日：2007-03-28

Applicant: Steven Keating

Inventor： Steven Keating

IPC: H01L21/302 ,  C08K13/02

CPC classification number: H01L21/02063 ,  C11D7/263 ,  C11D7/3218 ,  C11D7/3227 ,  C11D11/0047 ,  G03F7/425 ,  H01L21/31133

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括利用包含溶剂如乙二醇单丙基醚，无机碱，有机碱，铜腐蚀抑制剂和表面活性剂的清洁混合物来清洁聚合物残余物，有机牺牲填充材料和蚀刻的 或来自包含多孔氧化物电介质的微电子结构的镶嵌结构的未蚀刻光刻胶。

公开(公告)号：US09764220B2

公开(公告)日：2017-09-19

申请号：US13463424

申请日：2012-05-03

Applicant: Steven Keating ,  Neri Oxman

Inventor： Steven Keating ,  Neri Oxman

IPC: E04F15/10 ,  F16B7/00 ,  F16B9/02 ,  A63C19/04 ,  F16B4/00 ,  E01C13/04

CPC classification number: A63C19/04 ,  A63C2203/16 ,  E01C13/04 ,  E04F15/107 ,  E04F2290/044 ,  F16B4/002 ,  F16B7/00 ,  F16B9/02 ,  Y10T403/13 ,  Y10T403/25

Abstract: A reconfigurable device comprises flexible bladder that encloses a jammable material. The geometry of the device can be altered by unjamming the jammable material (making it flexible), changing the shape of the device while it is flexible, and then jamming the jammable material (making it rigid). In some applications of this invention, a joint connects rigid arms. The ends of the rigid arms are enclosed in the bladder. By varying the stiffness of the jammable material in the bladder, the stiffness of the joint can be controlled.

公开(公告)号：US20120280421A1

公开(公告)日：2012-11-08

申请号：US13463424

申请日：2012-05-03

Applicant: Steven Keating ,  Neri Oxman

Inventor： Steven Keating ,  Neri Oxman

IPC: B29C39/02 ,  F16B1/00 ,  B30B13/00

CPC classification number: A63C19/04 ,  A63C2203/16 ,  E01C13/04 ,  E04F15/107 ,  E04F2290/044 ,  F16B4/002 ,  F16B7/00 ,  F16B9/02 ,  Y10T403/13 ,  Y10T403/25

Abstract: In exemplary implementations of this invention, a reconfigurable device comprises flexible bladder that encloses a jammable material. The geometry of the device can be altered by unjamming the jammable material (making it flexible), changing the shape of the device while it is flexible, and then jamming the jammable material (making it rigid). In some applications of this invention, a joint connects rigid arms. The ends of the rigid arms are enclosed in the bladder. By varying the stiffness of the jammable material in the bladder, the stiffness of the joint can be controlled.

Abstract translation: 在本发明的示例性实施方式中，可重新配置的装置包括包围可燃材料的柔性气囊。 设备的几何形状可以通过使可疑材料（使其变得柔性）脱粘，改变设备的形状而变得柔软，然后阻塞可燃材料（使其变得刚性）。 在本发明的一些应用中，接头连接刚性臂。 刚性臂的端部封闭在膀胱中。 通过改变膀胱中的可塑材料的刚度，可以控制关​​节的刚度。

公开(公告)号：US07045407B2

公开(公告)日：2006-05-16

申请号：US10750054

申请日：2003-12-30

Applicant: Steven Keating ,  Chris Auth

Inventor： Steven Keating ,  Chris Auth

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/165

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract translation: 描述通过在衬底内注入具有电中性元素的衬底来形成非晶态蚀刻停止层的方法。 在衬底内使用电气中性的元件如果它们扩散到衬底内的其它区域，则防止元件的电干扰。 非晶蚀刻停止层可用作制造晶体管或诸如悬臂的其它器件的硬掩模。

公开(公告)号：US20060030104A1

公开(公告)日：2006-02-09

申请号：US11248737

申请日：2005-10-11

Applicant: Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

Inventor： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract translation: 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US20050040469A1

公开(公告)日：2005-02-24

申请号：US10946502

申请日：2004-09-20

Applicant: Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

Inventor： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

IPC: H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract translation: 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US07799139B2

公开(公告)日：2010-09-21

申请号：US11692349

申请日：2007-03-28

Applicant: Steven Keating

Inventor： Steven Keating

IPC: C11D7/50 ,  G03F7/42

CPC classification number: H01L21/02063 ,  C11D7/263 ,  C11D7/3218 ,  C11D7/3227 ,  C11D11/0047 ,  G03F7/425 ,  H01L21/31133

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括利用包含溶剂如乙二醇单丙基醚，无机碱，有机碱，铜腐蚀抑制剂和表面活性剂的清洁混合物来清洁聚合物残余物，有机牺牲填充材料和蚀刻的 或来自包含多孔氧化物电介质的微电子结构的镶嵌结构的未蚀刻光刻胶。