公开(公告)号：US08168488B2

公开(公告)日：2012-05-01

申请号：US13026103

申请日：2011-02-11

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在门上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。

公开(公告)号：US07709866B2

公开(公告)日：2010-05-04

申请号：US11821971

申请日：2007-06-26

Applicant: Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

Inventor： Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

IPC: H01L29/51 ,  H01L21/469

CPC classification number: H01L21/76804 ,  H01L21/76816 ,  H01L29/78

Abstract: In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

Abstract translation: 在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

公开(公告)号：US07927959B2

公开(公告)日：2011-04-19

申请号：US12286338

申请日：2008-09-30

Applicant: Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

Inventor： Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC: H01L21/467

CPC classification number: H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract translation: 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

公开(公告)号：US20080206991A1

公开(公告)日：2008-08-28

申请号：US11678059

申请日：2007-02-22

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76816

Abstract: A method of forming contacts to a transistor comprises depositing a dielectric layer on a substrate having the transistor, etching a first opening in the dielectric layer that contacts a gate stack of the transistor, depositing a sacrificial material in the first opening, and etching a second and a third opening in the dielectric layer that contact a source and a drain region of the transistor, wherein the second and third openings are etched after the first opening is etched. By etching the opening to the gate stack first, defects such as contact-to-gate shorts are reduced or eliminated.

Abstract translation: 形成与晶体管的接触的方法包括在具有晶体管的衬底上沉积电介质层，蚀刻介电层中接触晶体管栅极堆叠的第一开口，在第一开口中沉积牺牲材料，并蚀刻第二 以及在所述电介质层中与所述晶体管的源极和漏极区域接触的第三开口，其中在蚀刻所述第一开口之后蚀刻所述第二和第三开口。 首先通过蚀刻到栅极堆叠的开口，减少或消除诸如接触到栅极短路的缺陷。

公开(公告)号：US20060003597A1

公开(公告)日：2006-01-05

申请号：US10881052

申请日：2004-06-30

Applicant: Oleg Golonzka ,  Ajay Sharma ,  Nadia Rahhal-Orabi ,  Anthony Amour ,  James Chung

Inventor： Oleg Golonzka ,  Ajay Sharma ,  Nadia Rahhal-Orabi ,  Anthony Amour ,  James Chung

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L21/0217 ,  H01L21/0214 ,  H01L21/3143 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7843

Abstract: The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.

Abstract translation: 提高了集成电路的NMOS和PMOS区域的性能。 本发明的实施例包括形成针对n掺杂区域上的n掺杂区域优化的第一电介质层，并形成对p掺杂区域上的p掺杂区域优化的第二介电层。

公开(公告)号：US20110136314A1

公开(公告)日：2011-06-09

申请号：US13026103

申请日：2011-02-11

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L21/28

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在门上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。

公开(公告)号：US07655986B2

公开(公告)日：2010-02-02

申请号：US11644639

申请日：2006-12-21

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在门上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。

公开(公告)号：US20100022079A1

公开(公告)日：2010-01-28

申请号：US12567075

申请日：2009-09-25

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在门上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。

公开(公告)号：US20080150049A1

公开(公告)日：2008-06-26

申请号：US11644639

申请日：2006-12-21

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在门上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。

公开(公告)号：US07968395B2

公开(公告)日：2011-06-28

申请号：US12567075

申请日：2009-09-25

Applicant: Nadia Rahhal-Orabi

Inventor： Nadia Rahhal-Orabi

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/28247 ,  G06F3/04817 ,  G06F3/0486 ,  G06F3/04886 ,  H01L21/7624 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H04M1/72586 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract translation: 描述了用于减少与半导体器件中的栅极短路的接触以及所得到的半导体器件的方法。 在一个实施例中，栅极形成在衬底上，在栅极和衬底上形成接触，并且在栅极和触点之间形成绝缘体。 绝缘体可以通过在栅极上形成接触之后，通过氧化栅极而在接触和栅极之间形成电介质来形成。