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11.发明申请Per Thread Cacheline Allocation Mechanism in Shared Partitioned Caches in Multi-Threaded Processors 有权多线程处理器中共享分区缓存中的每线程Cacheline分配机制公开(公告)号：US20130304994A1
公开(公告)日：2013-11-14
申请号：US13466359
申请日：2012-05-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/0864
摘要： Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.
摘要翻译： 用于在多线程处理器的共享分区高速缓存中分配高速缓存行的系统和方法。 存储器管理单元被配置为确定与要在高速缓存中分配的处理线程相关联的高速缓存条目的地址相关联的属性。 配置寄存器被配置为基于所确定的属性来存储高速缓存分配信息。 分区寄存器被配置为存储用于将高速缓存分割成两个或更多个部分的分区信息。 基于配置寄存器和分区寄存器，缓存条目被分配到高速缓存的一部分中。
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12.发明申请System and Method of Executing Instructions in a Multi-Stage Data Processing Pipeline 有权多级数据处理管道中执行指令的系统和方法公开(公告)号：US20090070602A1
公开(公告)日：2009-03-12
申请号：US11850940
申请日：2007-09-06
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.
摘要翻译： 公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。 该装置还包括耦合到指令执行管线的控制逻辑电路。 控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。 控制逻辑电路还适于在执行解码指令期间执行至少一个非跳过级。
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13.发明授权System and method of executing instructions in a multi-stage data processing pipeline 有权在多级数据处理流水线中执行指令的系统和方法公开(公告)号：US08868888B2
公开(公告)日：2014-10-21
申请号：US11850940
申请日：2007-09-06
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.
摘要翻译： 公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。 该装置还包括耦合到指令执行管线的控制逻辑电路。 控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。 控制逻辑电路还适于在执行解码指令期间执行至少一个非跳过级。
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公开(公告)号：US20130179642A1
公开(公告)日：2013-07-11
申请号：US13398927
申请日：2012-02-17
CPC分类号： G06F12/0811 , G06F12/0888 , G06F12/1027
摘要： Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.
摘要翻译： 用于执行具有物理地址的非分配存储器访问指令的系统和方法。 系统包括处理器，一个或多个级别的高速缓存，存储器，翻译后备缓冲器（TLB）以及指定处理器的存储器访问和相关联的物理地址的存储器访问指令。 执行逻辑被配置为绕过存储器访问指令的TLB并且使用物理地址执行存储器访问，同时避免分配可能遇到未命中的一个或多个中间级别的高速缓存。
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公开(公告)号：US08464000B2
公开(公告)日：2013-06-11
申请号：US12039954
申请日：2008-02-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/121 , G06F2212/1016 , Y02D10/13
摘要： A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.
摘要翻译： 描述用于确定要替换的高速缓存行的系统。 在一个实施例中，系统包括包括多个高速缓存行的高速缓存。 该系统还包括被配置为识别用于替换的高速缓存行的标识符。 该系统还包括被配置为确定从增量器，高速缓存维护指令中选择的标识符的值的控制逻辑，或保持相同。
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公开(公告)号：US20130086360A1
公开(公告)日：2013-04-04
申请号：US13249284
申请日：2011-09-30
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
摘要翻译： 指令识别寄存器和存储器位置。 在由处理器执行指令时，从存储器位置加载一个物品，并执行移位和插入操作以移位寄存器中的数据并将该项目插入到寄存器中。
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公开(公告)号：US08260990B2
公开(公告)日：2012-09-04
申请号：US11942282
申请日：2007-11-19
CPC分类号： G06F13/161
摘要： A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.
摘要翻译： 公开了用于选择性地排除总线访问请求的系统和方法。 在一个实施例中，一种方法包括确定在处理器的逻辑电路处的总线单元访问设置。 该方法还包括基于总线单元访问设置选择性地排除总线单元访问请求。
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公开(公告)号：US08601234B2
公开(公告)日：2013-12-03
申请号：US11936269
申请日：2007-11-07
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.
摘要翻译： 本公开包括配置翻译后备缓冲器（TLB）的方法和系统。 在一个实施例中，TLB包括第一部分和第二部分。 可以响应于TLB配置指示符的值来选择性地禁用第一部分或第二部分。
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19.发明授权Dual function adder for computing a hardware prefetch address and an arithmetic operation value 失效双功能加法器，用于计算硬件预取地址和算术运算值公开(公告)号：US08185721B2
公开(公告)日：2012-05-22
申请号：US12041694
申请日：2008-03-04
CPC分类号： G06F9/383 , G06F9/3001
摘要： A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configured for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.
摘要翻译： 描述了包括双功能加法器的系统。 在一个实施例中，该系统包括加法器。 如果第一指令是硬件预取指令，则加法器被配置用于第一指令以确定用于硬件预取的地址。 如果第一指令是算术运算指令，则加法器还被配置用于第一指令从算术运算确定值。
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20.发明申请Dual Function Adder for Computing a Hardware Prefetch Address and an Arithmetic Operation Value 失效用于计算硬件预取地址和算术运算值的双功能加法器公开(公告)号：US20090228688A1
公开(公告)日：2009-09-10
申请号：US12041694
申请日：2008-03-04
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3001
摘要： A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configures for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.
摘要翻译： 描述了包括双功能加法器的系统。 在一个实施例中，该系统包括加法器。 如果第一指令是硬件预取指令，则加法器被配置用于第一指令以确定用于硬件预取的地址。 如果第一指令是算术运算指令，则加法器进一步配置用于从算术运算确定值的第一指令。
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