Abstract:
Significant reductions in transfer smear for charge sweep device imagers is made possible by performing the charge sweep operation during only the line retrace period of the operating cycle of the imager. Complete elimination of transfer smear is then possible by using an optical means for blocking the imager from incident illumination during said line retrace periods.
Abstract:
An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.
Abstract:
A CCD imager of field transfer type having an image register statically clocked during image integration in a number of phases greater than it is dynamically clocked with during field transfer to a field storage register, when the image register and the field storage register are clocked in synchronous phase with each other.
Abstract:
A CCD imaging system is provided, including a short focal length lens for accepting light from the scene to be imaged and a charge storage medium having a charge storage substrate that is curved in a selected nonplanar focal surface profile and located a selected distance from the lens with the focal surface facing the lens, the focal surface profile and the lens-to-substrate distance selected such that the light accepted by the lens is in focus at the position of the substrate. There is provided a support substrate on which the nonplanar charge storage substrate is supported to maintain the selected surface profile of the charge storage substrate. An array of pixels defined in the charge storage substrate by pixel interconnections is supported on the front side of the substrate, such that exposure of the substrate to light from the scene through the lens produces charge packets in the pixels, with the pixel interconnection providing selective electronic temporal control of transfer of charge packets from one pixel to another in the substrate. The invention provides a technique for suppressing dark current charge packet generation in the substrate pixels. An output circuit converts the charge packets in the pixels to an electrical pixel signal of output pixel values based on the light from the scene. A plurality of pixel values together form an image frame, the output pixel values being produced at a rate corresponding to the image frame rate, R.
Abstract:
The wafer thickness of a CCD front illuminated silicon wafer is reduced to about ten to twenty microns, the Al substrate is removed and a 5-35 nanometer silicon oxide layer is produced on the thinned back of the silicon wafer followed by implanting boron ions within the back surface to a depth up to about ten nanometers. Furnace annealing the wafer is now carried out, and the Al substrate is redeposited to enable the formation of gate contacts.
Abstract:
An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B. The output image frame sequence is characterized by noise-limited resolution of at least a minimum number, N.sub.M, of line pairs per millimeter, referred to the charge-coupled imaging device pixel array, in an imaged scene as a function of illuminance of the input light impinging the charge-coupled imaging device pixels.
Abstract:
A target for vidicons and image intensifier tubes include a potential barrier less than about 1500 A from an input signal sensing surface. The targets also include various passivation means for stabilizing the energy level configuration along the input signal sensing surface by substantially fixing the valence or conduction band along that surface relative to the Fermi level.