利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

370 条记录 (耗时 0.031 秒)

    Semiconductor structures including vertical diode structures and methods for making the same
    12.
    发明授权
    Semiconductor structures including vertical diode structures and methods for making the same 有权
    包括垂直二极管结构的半导体结构及其制造方法

    公开(公告)号：US08034716B2

    公开(公告)日：2011-10-11

    申请号：US12434212

    申请日：2009-05-01

    申请人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung T. Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

    发明人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung T. Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

    IPC分类号： H01L21/44

    CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

    摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

    摘要翻译： 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

    Three-dimensional container diode for use with multi-state material in a non-volatile memory cell
    14.
    发明授权
    Three-dimensional container diode for use with multi-state material in a non-volatile memory cell 有权
    用于非易失性存储单元中的多态材料的三维容器二极管

    公开(公告)号：US06429449B1

    公开(公告)日：2002-08-06

    申请号：US09569992

    申请日：2000-05-12

    申请人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

    发明人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

    IPC分类号： H01L4700

    CPC分类号： H01L27/24 ,  H01L27/1021

    摘要： A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

    摘要翻译： 用于将电流传送到存储器单元中的多状态存储器元件的垂直取向的二极管。 垂直二极管可以设置在从硅或氧化物层的顶部向下延伸的二极管容器中，并且可以由靠近二极管容器的内表面设置的硅和/或金属层的组合形成。 多状态存储元件可以由二极管上方的多态材料（例如硫族化物）形成以完成存储单元。

    Method of making memory cell incorporating a chalcogenide element
    20.
    发明授权
    Method of making memory cell incorporating a chalcogenide element 失效
    制备含有硫属元素元素的记忆单元的方法

    公开(公告)号：US5970336A

    公开(公告)日：1999-10-19

    申请号：US961563

    申请日：1997-10-30

    申请人： Graham R. Wolstenholme ,  Fernando Gonzalez ,  Russell C. Zahorik

    发明人： Graham R. Wolstenholme ,  Fernando Gonzalez ,  Russell C. Zahorik

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L21/8242

    CPC分类号： H01L27/24 ,  H01L21/28512 ,  H01L21/76807 ,  H01L21/8229 ,  H01L27/1021

    摘要： A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

    摘要翻译： 公开了并入有硫属元素元素的记忆体及其制造方法。 在该方法中，掺杂硅衬底设置有两个或多个多晶硅插塞以形成二极管存储单元的阵列。 一个氮化硅层设置在插头上。 使用多隔离工艺，在氮化硅中形成小孔以暴露一部分多晶硅插塞。 通过在氮化硅层上沉积一层硫族化物材料并使用CMP将硫属化物层平坦化成氮化硅层，将硫属化物材料设置在孔中。 随后将一层TiN沉积在插塞上，随后是金属化层。 然后对TiN和金属化层进行掩模和蚀刻以限定存储单元区域。