公开(公告)号：US20100184258A1

公开(公告)日：2010-07-22

申请号：US12748836

申请日：2010-03-29

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： H01L21/82

CPC分类号： H01L23/5226 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683 ,  H01L45/1691 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

摘要翻译： 一种用于制造具有有限尺寸有源面积的非易失性电阻性存储元件的存储单元的方法和装置。 该方法包括提供电介质体积并在介电体积内形成插塞开口的第一步骤。 然后在开口的下部形成导电材料的凹形插塞，并且沿着开口的上部的侧壁形成介电隔离件。 间隔件是圆柱形的并且具有中心孔。 接触塞随后形成在中心孔内，该接触插塞电耦合到凹形插头。 接触插头可以包括存储元件，或者可以将附加的存储元件施加在接触插头上。

公开(公告)号：USRE40842E1

公开(公告)日：2009-07-14

申请号：US11008755

申请日：2004-12-09

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： H01L29/76

CPC分类号： H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

摘要： Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

公开(公告)号：US20090152737A1

公开(公告)日：2009-06-18

申请号：US12392886

申请日：2009-02-25

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： H01L29/06 ,  H01L45/00

CPC分类号： H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

摘要： Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

摘要翻译： 描述了环状，线性和点接触结构，其显示出比常规圆形接触插塞大大降低由光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。

公开(公告)号：US06831330B2

公开(公告)日：2004-12-14

申请号：US10158504

申请日：2002-05-30

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： H01L2976

CPC分类号： H01L23/5226 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683 ,  H01L45/1691 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

摘要翻译： 一种用于制造具有有限尺寸有源区的非易失性电阻性存储元件的存储单元的方法和装置。 该方法包括提供电介质体积并在介电体积内形成插塞开口的第一步骤。 然后在开口的下部形成导电材料的凹形插塞，并且沿着开口的上部的侧壁形成介电隔离件。 间隔件是圆柱形的并且具有中心孔。 接触塞随后形成在中心孔内，该接触插塞电耦合到凹形插头。 接触插头可以包括存储元件，或者可以将附加的存储元件施加在接触插头上。

公开(公告)号：US06111264A

公开(公告)日：2000-08-29

申请号：US970180

申请日：1997-11-13

申请人： Graham R. Wolstenholme ,  Steven T. Harshfield ,  Raymond A. Turi ,  Fernando Gonzalez ,  Guy T. Blalock ,  Donwon Park

发明人： Graham R. Wolstenholme ,  Steven T. Harshfield ,  Raymond A. Turi ,  Fernando Gonzalez ,  Guy T. Blalock ,  Donwon Park

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L47/00

CPC分类号： H01L45/1691 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

摘要翻译： 特别是制造用于硫族化物记忆体的超小孔或接触物的方法，其特征在于半导体器件中，其中一次性间隔物用于制造超小孔或接触。 如此限定的孔具有约500至4000埃的最小横向尺寸。 然后可以将如此限定的孔用于制造硫族化物存储器单元或其它半导体器件。

公开(公告)号：US07102150B2

公开(公告)日：2006-09-05

申请号：US09853233

申请日：2001-05-11

申请人： Steven T. Harshfield ,  David Q. Wright

发明人： Steven T. Harshfield ,  David Q. Wright

IPC分类号： H01L47/00

CPC分类号： H01L21/288 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/165

摘要： An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

公开(公告)号：US07078755B2

公开(公告)日：2006-07-18

申请号：US10212544

申请日：2002-08-05

申请人： Allen McTeer ,  Steven T. Harshfield

发明人： Allen McTeer ,  Steven T. Harshfield

IPC分类号： H01L27/108

CPC分类号： H01L21/76841 ,  H01L21/288 ,  H01L21/7687 ,  H01L21/76877 ,  H01L21/76879 ,  H01L27/10855 ,  H01L28/75 ,  H01L28/90 ,  H01L28/91 ,  Y10S438/902

摘要： Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.

公开(公告)号：US06440837B1

公开(公告)日：2002-08-27

申请号：US09617297

申请日：2000-07-14

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： H01L214763

CPC分类号： H01L45/122 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691

摘要： Annular and linear contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

摘要翻译： 描述了环状和线性接触结构，其显示出比常规圆形接触插塞大大降低由于光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。

公开(公告)号：US5818749A

公开(公告)日：1998-10-06

申请号：US804864

申请日：1997-02-24

申请人： Steven T. Harshfield

发明人： Steven T. Harshfield

IPC分类号： G11C17/16 ,  H01L27/06 ,  H01L27/24 ,  G11C17/06

CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C17/16 ,  H01L27/0629 ,  H01L27/24 ,  G11C2213/72

摘要： A memory array using structure changing memory elements in a reverse biased diode array is disclosed. A memory cell is programmed and read by reverse biasing the diode to overcome the diode's breakdown voltage. The disclosed reversed biased diode array exhibits much less substrate current leakage than a similar forward biased diode array.

摘要翻译： 公开了一种使用反向偏置二极管阵列中的结构改变存储元件的存储器阵列。 通过反向偏置二极管来克服二极管的击穿电压来对存储单元进行编程和读取。 所公开的反向偏置二极管阵列表现出比类似的正向偏置二极管阵列少得多的衬底电流泄漏。

公开(公告)号：US5719418A

公开(公告)日：1998-02-17

申请号：US604006

申请日：1996-02-20

申请人： Nanseng Jeng ,  Steven T. Harshfield ,  Paul J. Schuele

发明人： Nanseng Jeng ,  Steven T. Harshfield ,  Paul J. Schuele

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10873 ,  Y10S148/014

摘要： A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide. The nitride and oxide is removed from the sidewalls, and a conductive layer is formed over the exposed trench sidewalls, the trench bottom being insulated from the conductive layer by the oxide layer over the bottom of the trench. The oxide on the bottom of the trench contacts the field oxide. The contact is isolated from the substrate along the trench bottom and the second sidewall, making contact with the substrate only in the area of the first sidewall.

摘要翻译： 用于在半导体器件上形成与半导体衬底的接触的结构和工艺包括在半导体衬底上和场氧化物区域上形成图案化掩模的步骤，然后蚀刻半导体衬底和场氧化物区域以形成沟槽。 沟槽包括底部和由硅组成的第一侧壁和包括场氧化物的第二侧壁。 蚀刻步骤去除衬底中的掺杂区域的一部分。 接下来，在衬底上形成覆盖氮化物层和覆盖氧化物层，并且在氮化物层和氧化物层上执行衬垫蚀刻，在第一和第二侧壁上留下氮化物和氧化物。 沟槽底部被氧化以在沟槽的底部形成一层氧化物，从而使沟槽底部绝缘，并且氧化物侵蚀在侧壁上的氮化物和氧化物之下，以与场氧化物结合。 从侧壁去除氮化物和氧化物，并且在暴露的沟槽侧壁上形成导电层，沟槽底部通过沟槽底部的氧化物层与导电层绝缘。 沟槽底部的氧化物与场氧化物接触。 接触件沿着沟槽底部和第二侧壁与衬底隔离，仅在第一侧壁的区域中与衬底接触。