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11.发明授权Process for manufacturing thick suspended structures of semiconductor material 有权用于制造半导体材料的厚悬浮结构的方法公开(公告)号：US07871894B2
公开(公告)日：2011-01-18
申请号：US11541376
申请日：2006-09-27
IPC分类号： H01L21/76
CPC分类号： B81C1/00158 , B81B2201/025 , B81B2203/0109 , B81B2203/0315
摘要： A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.
摘要翻译： 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。
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12.发明授权Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 有权制造具有SOI绝缘阱和半导体晶片的半导体晶片的制造方法公开(公告)号：US09105690B2
公开(公告)日：2015-08-11
申请号：US13023039
申请日：2011-02-08
IPC分类号： H01L29/08 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76264 , H01L21/7682
摘要： A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.
摘要翻译： 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介电层。
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13.发明授权Method for forming buried cavities within a semiconductor body, and semiconductor body thus made 有权在半导体本体内形成掩埋空穴的方法以及由此制成的半导体本体公开(公告)号：US08420428B2
公开(公告)日：2013-04-16
申请号：US12873685
申请日：2010-09-01
CPC分类号： B81C1/00047 , B01L3/502707 , B01L7/52 , B01L2200/12 , B01L2300/0636 , B01L2300/0645 , B01L2300/0816 , B01L2300/1827 , B81B2201/0264 , B81B2203/0315
摘要： A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
摘要翻译： 一种用于在半导体主体内形成掩埋空腔的方法，设想了以下步骤：提供具有由半导体材料制成的体区的晶片; 在本体区域中挖掘在它们的半导体材料壁之间划定的沟槽; 形成用于在脱氧气氛存在下关闭所述沟槽的闭合层，以便使所述沟槽内的脱氧气氛充满; 进行热处理，使壁的半导体材料迁移并形成掩埋腔。 此外，在进行热处理之前，在沟槽顶部的闭合层上形成基本上不透氢的阻挡层。
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公开(公告)号：US07846811B2
公开(公告)日：2010-12-07
申请号：US11448589
申请日：2006-06-06
IPC分类号： H01L21/76
CPC分类号： H01L21/76264 , H01L21/3247
摘要： In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.
摘要翻译： 在制造SOI晶片的工艺中，设想以下步骤：在具有前表面的半导体材料的整体式中，与前表面相距一定距离地延伸的掩埋空腔， 所述整体体的表面区域，所述表面区域被块体区域包围并形成悬浮在所述掩埋空腔上方的柔性膜; 通过整体式的主体形成至少一个到达埋入腔的进入通道; 并且用绝缘区域均匀地填充掩埋腔。 表面区域是连续的，由半导体材料的单一部分形成，并且掩埋腔被包含并在整体体内完全绝缘; 在形成掩埋腔的步骤之后，进行形成至少一个进入通道的步骤。
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15.发明授权Method for forming buried cavities within a semiconductor body, and semiconductor body thus made 有权在半导体本体内形成掩埋空穴的方法以及由此制成的半导体本体公开(公告)号：US07811848B2
公开(公告)日：2010-10-12
申请号：US11486387
申请日：2006-07-12
CPC分类号： B81C1/00047 , B01L3/502707 , B01L7/52 , B01L2200/12 , B01L2300/0636 , B01L2300/0645 , B01L2300/0816 , B01L2300/1827 , B81B2201/0264 , B81B2203/0315
摘要： A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
摘要翻译： 一种用于在半导体主体内形成掩埋空腔的方法，设想了以下步骤：提供具有由半导体材料制成的体区的晶片; 在本体区域中挖掘在它们的半导体材料壁之间划定的沟槽; 形成用于在脱氧气氛存在下关闭所述沟槽的闭合层，以便使所述沟槽内的脱氧气氛充满; 进行热处理，使壁的半导体材料迁移并形成掩埋腔。 此外，在进行热处理之前，在沟槽顶部的闭合层上形成基本上不透氢的阻挡层。
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16.发明申请Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 有权制造具有SOI绝缘阱和半导体晶片的半导体晶片的制造方法公开(公告)号：US20080029817A1
公开(公告)日：2008-02-07
申请号：US11879738
申请日：2007-07-17
IPC分类号： H01L21/764 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/7682
摘要： A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.
摘要翻译： 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介电层。
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公开(公告)号：US09170183B2
公开(公告)日：2015-10-27
申请号：US13621176
申请日：2012-09-15
CPC分类号： B01L3/502715 , B01L2200/025 , B01L2200/027 , B01L2200/028 , B01L2200/0684 , B01L2300/0645 , B01L2300/087 , B01L2400/049 , G01N5/02 , G01N29/022 , G01N33/54366 , G01N33/5438 , G01N33/76 , G01N2035/00237
摘要： A device for detecting the concentration of biological materials, is formed in a body having a plurality of fluidic paths connectable to a multi-microbalance structure carrying a plurality of microbalances, each microbalance having a sensitive portion facing a reaction chamber. The body and the multi-microbalance structure are configured to be mechanically coupled together and each microbalance is configured to be coupled to a respective fluidic path. Each fluidic path includes an inlet, a duct and a liquid waste, each duct being configured to be coupled with a respective reaction chamber. The plurality of fluidic paths and microbalances form at least one first and one second reference cells and one first sample cell.
摘要翻译： 用于检测生物材料浓度的装置形成在具有可连接到多微量平衡结构的多个微量平衡结构的多个流体路径的主体中，每个微量天平具有面向反应室的敏感部分。 主体和多微平衡结构被配置为机械耦合在一起，并且每个微量天平被配置为耦合到相应的流体路径。 每个流体路径包括入口，管道和液体废物，每个管道被配置为与相应的反应室联接。 多个流体路径和微量平衡形成至少一个第一和第二参考单元和一个第一样品池。
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18.发明授权Integrated chemical microreactor with large area channels and manufacturing process thereof 有权具有大面积通道的集成化学微反应器及其制造工艺公开(公告)号：US07732192B2
公开(公告)日：2010-06-08
申请号：US11743062
申请日：2007-05-01
IPC分类号： C12N1/10
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/00828 , Y10T436/114998
摘要： The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
摘要翻译： 微反应器具有半导体材料体; 一个大面积的埋藏通道延伸到身体并具有墙壁; 覆盖通道壁的绝缘材料的涂层; 一个在主体顶部延伸并向上关闭通道的隔膜。 隔膜由完全环绕绝缘材料的掩模部分的半导体层形成。
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公开(公告)号：US08499613B2
公开(公告)日：2013-08-06
申请号：US13016086
申请日：2011-01-28
申请人： Federico Giovanni Ziglioli , Amedeo Maierna , Flavio Francesco Villa , Ubaldo Mastromatteo , Gabriele Barlocchi
发明人： Federico Giovanni Ziglioli , Amedeo Maierna , Flavio Francesco Villa , Ubaldo Mastromatteo , Gabriele Barlocchi
IPC分类号： G01N7/04
CPC分类号： G01N33/0009
摘要： A cartridge-like chemical sensor is formed by a housing having a base and a cover fixed to the base and provided with an input opening, an output hole and a channel for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board carrying an integrated circuit having a sensitive region open toward the channel and of a material capable to bind with target chemicals in the gas to be analyzed. A fan is arranged in the housing, downstream of the integrated device, for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit.
摘要翻译： 盒式化学传感器由壳体形成，壳体具有固定到基座的基部和盖，并且设置有用于待分析气体的输入开口，输出孔和通道。 通道在输入开口和输出孔之间的盖中延伸，并且面向承载具有朝向通道开口的敏感区域的集成电路的印刷电路板和能够与要分析的气体中的目标化学物质结合的材料。 在集成装置的下游的壳体内设置风扇，用于在分析后吸入气体，并且是集成电路的热控制系统的一部分。
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20.发明授权公开(公告)号：US07348257B2
公开(公告)日：2008-03-25
申请号：US11225883
申请日：2005-09-13
IPC分类号： H01L21/30
CPC分类号： H01L21/3247 , H01L21/3043 , H01L21/76251 , H01L21/76259
摘要： A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.
摘要翻译： 一种工艺使用半导体处理技术制造晶片。 在第一晶片的顶表面上形成接合层; 在属于第二晶片的半导体材料的衬底中挖出深沟槽。 半导体材料的顶层形成在衬底的顶部上，以封闭顶部的深沟槽并形成至少一个埋入空腔。 第二晶片的顶层通过结合层结合到第一晶片。 对这两个晶片进行热处理，其导致顶层的至少一部分与第一晶片的接合和掩埋腔的加宽。 以这种方式，将结合到第一晶片的顶层的部分与第二晶片的其余部分分离，以形成复合晶片。
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