公开(公告)号：US06826111B2

公开(公告)日：2004-11-30

申请号：US10186327

申请日：2002-06-28

申请人： Ralf Schneider ,  Evangelos Stavrou ,  Tobias Hartner ,  Norbert Wirth

发明人： Ralf Schneider ,  Evangelos Stavrou ,  Tobias Hartner ,  Norbert Wirth

IPC分类号： G11C800

CPC分类号： G11C29/36 ,  G11C29/18

摘要： A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

摘要翻译： 一种方法包括提供具有至少一个存储单元阵列的半导体存储器件。 存储单元阵列具有以矩阵状排列的多个存储单元。 每个存储单元被分配一个物理地址和一个电子地址。 该方法还包括将要寻址的存储器单元的物理地址输入到半导体存储器件的地址输入设备中，将输入物理地址解码为由地址解码器器件寻址的存储器单元的分配电地址 并且将电地址输出到存储单元阵列以便寻址存储单元。

公开(公告)号：US06754869B2

公开(公告)日：2004-06-22

申请号：US09909390

申请日：2001-07-19

申请人： Thorsten Bucksch ,  Ralf Schneider

发明人： Thorsten Bucksch ,  Ralf Schneider

IPC分类号： G06F1100

CPC分类号： G11C29/028 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012

摘要： For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.

摘要翻译： 对于测试，参考时钟信号被施加到具有固定延迟的第一延迟路径和具有可变延迟的第二延迟路径。 延迟路径连接到时钟电路的输入以启动数据传输，并分别施加时钟信号和数据信号。 可变延迟设置在[tF-nDeltat / 2; tF + nDeltat / 2]。 固定延迟tF至少为nDeltat / 2。 对于校准，可变延迟和固定延迟的设置范围各自增加到k倍值，并且可变延迟以n = 0的步长增加，直到检测到三相变化。 第一相循环完成时n的值对应于建立时间的可变延迟，第三相循环完成时n的值对应于保持时间的可变延迟。

公开(公告)号：US06734695B2

公开(公告)日：2004-05-11

申请号：US10094890

申请日：2002-03-06

申请人： Thilo Schaffroth ,  Ralf Schneider

发明人： Thilo Schaffroth ,  Ralf Schneider

IPC分类号： G01R3126

CPC分类号： G01R21/10

摘要： A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a selected connecting pin. Since there are normally no unused connecting pins, in, for example, present-day large scale integrated components, the connected module is disconnected from a selected connecting pin for a specific time period, and the divided measurement voltage is passed to the connecting pin. This is done by use of a controller, which operates appropriate switches. This method is preferably used for memory components such as DRAM, SRAM etc.

摘要翻译： 描述了一种方法和半导体部件，其中待测量的内部电压经由匹配的分压器被分压，并被传递到所选择的连接引脚。 由于通常没有未使用的连接引脚，例如在当前的大规模集成部件中，所连接的模块在特定时间段内与所选择的连接引脚断开，并且分开的测量电压被传递到连接引脚。 这通过使用控制器来完成，该控制器操作适当的开关。 该方法优选用于诸如DRAM，SRAM等存储器组件。

公开(公告)号：US09029594B2

公开(公告)日：2015-05-12

申请号：US12471528

申请日：2009-05-26

申请人： Sven Michael Hansen ,  Ralf Schneider ,  Bernd Schwethelm ,  Rolf Schiefer ,  Jürgen Dreher

发明人： Sven Michael Hansen ,  Ralf Schneider ,  Bernd Schwethelm ,  Rolf Schiefer ,  Jürgen Dreher

IPC分类号： C07C263/00 ,  C07C263/10 ,  C07C263/20

CPC分类号： C07C263/10 ,  C07C263/20 ,  C07C265/14 ,  C07C265/12

摘要： Isocyanates are produced in the gas phase and by-products such as ammonium halides are selectively separated from the gas phase by desublimation.

摘要翻译： 异氰酸酯在气相中产生，并且副产物例如卤化铵通过公开选择性地与气相分离。

公开(公告)号：US20080166575A1

公开(公告)日：2008-07-10

申请号：US11913529

申请日：2006-05-03

申请人： Klaus-Dieter Nittel ,  Ralf Schneider ,  Andreas Lang

发明人： Klaus-Dieter Nittel ,  Ralf Schneider ,  Andreas Lang

IPC分类号： B32B15/04 ,  B21B45/02 ,  C23C28/00

CPC分类号： C25D11/36 ,  C23C22/17 ,  C23C22/188 ,  C23C22/22 ,  Y10T428/31678

摘要： The invention relates to a method for preparing metallic workpieces for cold forming by contacting the metallic surfaces thereof with an aqueous acid phosphating solution so as to embody at least one phosphate coating and then coating the phosphate-coated surfaces with at least one lubricant in order to embody at least one lubricant layer. According to the inventive method, the phosphating solution essentially contains only calcium, magnesium, or/and manganese as cations that are selected among cations of main group 2 and subgroups 1, 2, and 5 to 8 of the periodic table of chemical elements in addition to phosphate. Furthermore, an alkaline earth metal-containing phosphating solution is free from fluoride and complex fluoride while the phosphating process is carried out electrolytically. The invention further relates to a metallic workpiece that is coated accordingly as well as the use of workpieces coated in said manner.

摘要翻译： 本发明涉及一种通过使其金属表面与酸性磷酸盐水溶液接触来制备用于冷成型的金属工件的方法，以便体现至少一种磷酸盐涂层，然后用至少一种润滑剂涂覆磷酸盐涂覆的表面，以便 至少涂抹一层润滑剂层。 根据本发明的方法，磷化溶液基本上仅含有钙，镁或锰作为阳离子，其阳离子另外选自化学元素周期表第2族和第1,2族和第5至8族的阳离子 到磷酸盐。 此外，在电解进行磷化处理的同时，含碱土金属的磷酸盐溶液不含氟化物和络合氟化物。 本发明还涉及相应地涂覆的金属工件，以及使用以所述方式涂覆的工件。

公开(公告)号：US07203883B2

公开(公告)日：2007-04-10

申请号：US11086655

申请日：2005-03-23

申请人： Aurel von Campenhausen ,  Marcin Gnat ,  Joerg Vollrath ,  Ralf Schneider

发明人： Aurel von Campenhausen ,  Marcin Gnat ,  Joerg Vollrath ,  Ralf Schneider

IPC分类号： G06F11/00

CPC分类号： G11C29/50012 ,  G01R31/3016 ,  G11C29/02

摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。

公开(公告)号：US07196572B2

公开(公告)日：2007-03-27

申请号：US11123226

申请日：2005-05-06

申请人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

发明人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

IPC分类号： G05F1/10

CPC分类号： G11C11/4074 ,  G11C5/145

摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

摘要翻译： 集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。 包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。 控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值 输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。 结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

公开(公告)号：US20060090669A1

公开(公告)日：2006-05-04

申请号：US10509586

申请日：2003-04-02

申请人： Klaus-Dieter Nittel ,  Ralf Schneider

发明人： Klaus-Dieter Nittel ,  Ralf Schneider

IPC分类号： C23C18/38

CPC分类号： C23C18/38 ,  C23C18/48

摘要： The invention relates to an aqueous concentrate which is stable with respect to freezing and defrosting and which contains at least one water-soluble or water-dispersible copper compound and, optionally, also a water-soluble or water-dispersible tin compound for use in a diluted state as a bath for the currentless copper plating or bronze plating of objects, especially metal objects such as iron or steel wires, characterised in that it contains at least one complexed water-soluble or water-dispersed copper compound. The invention also relates to an aqueous bath which contains at least one aqueous or water-dispersible copper compound and, optionally, a water-soluble or water-dispersible tin compound for the currentless copper plating of objects in addition to at least one brightening agent and which has an adjusted pH value of less than 2.5. The invention also relates to a method for currentless copper plating or bronze plating of an object, especially a metallic object.

摘要翻译： 本发明涉及一种在冷冻和除霜方面稳定的含水浓缩物，其含有至少一种水溶性或水分散性铜化合物，以及任选地还可用于水溶性或水分散性锡化合物 稀释状态作为用于对象，特别是诸如铁或钢丝的金属物体的无电镀铜或青铜镀层的浴，其特征在于其含有至少一种络合的水溶性或水分散的铜化合物。 本发明还涉及含有至少一种水性或水分散性铜化合物和任选的水溶性或水分散性锡化合物的水浴，其用于除了至少一种增亮剂以外的物体的无电镀铜， 其pH值小于2.5。 本发明还涉及一种用于对象，特别是金属物体的无电镀铜或镀青铜的方法。

公开(公告)号：US20050213269A1

公开(公告)日：2005-09-29

申请号：US11092885

申请日：2005-03-29

申请人： Joerg Vollrath ,  Marcin Gnat ,  Aurel Campenhausen ,  Ralf Schneider

发明人： Joerg Vollrath ,  Marcin Gnat ,  Aurel Campenhausen ,  Ralf Schneider

IPC分类号： G01R19/165 ,  G11C5/14 ,  G11C11/4074 ,  G11C29/00 ,  G11C29/48 ,  G11C29/50 ,  H02H3/00

CPC分类号： G11C5/143 ,  G01R19/16552 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5004

摘要： An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

摘要翻译： 集成电路包括具有用于施加参考电压的第一输入端子的电流发生器电路和用于施加由外部施加的电源电压内部由电压发生器电路产生的输入电压的第二输入端子。 电流发生器电路通过互连连接到输出端子。 在集成电路的测试操作状态下，第一电流在互连上流动。 电流发生器电路在随后的第二测试周期中在测试操作状态的第一测试周期和第二部分电流中产生第一部分电流。 部分电流各自叠加在互连上的第一电流上。 因此，在测试操作状态期间，输出端子发生三个电流。 电流发生器电路的内部产生的输入电压由三个电流和参考电压确定。

公开(公告)号：US20050135163A1

公开(公告)日：2005-06-23

申请号：US11008159

申请日：2004-12-10

申请人： Ralf Schneider ,  Jurgen Auge ,  Stephan Schroder ,  Manfred Proll

发明人： Ralf Schneider ,  Jurgen Auge ,  Stephan Schroder ,  Manfred Proll

IPC分类号： G11C7/00 ,  G11C11/407 ,  G11C16/04 ,  G11C29/44

CPC分类号： G11C29/44 ,  G11C11/401 ,  G11C2029/1208 ,  G11C2029/4402

摘要： An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit. The integrated circuit enables the storage of external operating parameters of the integrated circuit.

摘要翻译： 一种集成电路包括用于产生编程信号（PS 1，...，PS 4）的编程电路（10），其具有用于施加控制电压（ES）的第一输入端（E 1），第二输入端 ），用于施加参考电压（Vref），具有可编程开关（35 ...，38）和输出端子（A 1，...，A 4）的存储电路（30）。 当控制电压（ES）超过由参考电压形成的预定阈值电压时，编程电路在每种情况下产生编程信号（PS 1，...，PS 4）。 编程信号（PS 1，...，PS 4）的数量取决于超过控制电压（ES）的阈值电压的大小。 编程信号用于对可编程开关（35，...，38）进行编程。 可编程开关的编程状态可以通过集成电路的输出端子（A 1，...，A 4）读出。 集成电路可以存储集成电路的外部工作参数。