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114 条记录 (耗时 0.034 秒)

    Dissolvable dielectric method
    12.
    发明授权
    Dissolvable dielectric method 失效
    溶解介电法

    公开(公告)号：US5953626A

    公开(公告)日：1999-09-14

    申请号：US659166

    申请日：1996-06-05

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/7682

    摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

    摘要翻译： 一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。 随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。 在本发明的一个实施例中，在阻挡层上形成第一互连电平。 然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。 在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。 除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。 临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。 在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。 如果需要，气隙电介质可以与多于两个级别的互连一起使用。

    Integrated circuit having horizontally and vertically offset interconnect lines
    14.
    发明授权
    Integrated circuit having horizontally and vertically offset interconnect lines 失效
    集成电路具有水平和垂直偏移的互连线

    公开(公告)号：US5854131A

    公开(公告)日：1998-12-29

    申请号：US655245

    申请日：1996-06-05

    申请人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford Jr. ,  Fred N. Hause ,  William S. Brennan

    发明人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford Jr. ,  Fred N. Hause ,  William S. Brennan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L21/44

    CPC分类号： H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002

    摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.

    摘要翻译： 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。 因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。 交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。 此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。 根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。 封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

    Semiconductor interlevel dielectric having a polymide for producing air gaps
    17.
    发明授权
    Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
    具有用于产生气隙的聚酰亚胺的半导体层间电介质

    公开(公告)号：US5783481A

    公开(公告)日：1998-07-21

    申请号：US659167

    申请日：1996-06-05

    申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002

    摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.

    摘要翻译： 提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。 电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。 当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。 空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。 介电沉积工艺优选包括两个沉积循环。 使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。 聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

    Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
    20.
    发明授权
    Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 失效
    制造由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区域的方法

    公开(公告)号：US5899727A

    公开(公告)日：1999-05-04

    申请号：US642155

    申请日：1996-05-02

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76205 ,  H01L21/76229

    摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

    摘要翻译： 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。