公开(公告)号：US06228703B1

公开(公告)日：2001-05-08

申请号：US09209648

申请日：1998-12-10

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： A method of fabricating a mixed mode semiconductor device. A semiconductor substrate having a device isolation region and a gate oxide layer formed thereon is provided. A first conductive layer is formed to cover the device isolation region and the gate oxide layer. A dielectric layer if formed over the device isolation region to cover a part of the first conductive layer. A second conductive layer is formed on the dielectric layer and the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a capacitor and a gate.

摘要翻译： 一种制造混合模式半导体器件的方法。 提供了具有器件隔离区域和形成在其上的栅极氧化物层的半导体衬底。 形成第一导电层以覆盖器件隔离区域和栅极氧化物层。 如果形成在器件隔离区上以覆盖第一导电层的一部分的介电层。 在介电层和第一导电层上形成第二导电层。 将第二导电层和第一导电层图案化以形成电容器和栅极。

公开(公告)号：US5950097A

公开(公告)日：1999-09-07

申请号：US698828

申请日：1996-08-16

申请人： Kuang-Yeh Chang ,  Yowjuang William Liu ,  Mark I. Gardner ,  Frederick N. Hause

发明人： Kuang-Yeh Chang ,  Yowjuang William Liu ,  Mark I. Gardner ,  Frederick N. Hause

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/36

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76294

摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

摘要翻译： 氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体本体的表面的部分。 然后，外延区域从半导体本体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

公开(公告)号：US5930628A

公开(公告)日：1999-07-27

申请号：US093691

申请日：1998-06-09

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/11543 ,  H01L27/11546

摘要： A method for fabricating a one-time programmable read only memory includes forming a spacer to cover the sides of the periphery transistor gate before patterning the control gate, then patterning the polysilicon layer to form a floating gate, and then forming a heavily concentrated ion implantation area in the substrate beneath the sides of the floating gate. Since the spacer is deposited on the sidewalls of the polysilicon layer within the peripheral area, but not the memory cell area, the efficiency of programming is improved. In addition, there is no need for extra ion implantation processes for make up for the lower programming efficiency caused by the spacers. Furthermore, the leakage current that is caused by the damage to the field oxide generated during the etching back process for forming the spacer is eliminated.

摘要翻译： 一种制造一次性可编程只读存储器的方法包括在图案化控制栅极之前形成间隔物以覆盖外围晶体管栅极的侧面，然后构图多晶硅层以形成浮置栅极，然后形成大量浓缩的离子注入 位于浮动门侧面底部的区域。 由于间隔物沉积在外围区域内的多晶硅层的侧壁上，而不是存储单元区域，因此编程效率得到改善。 此外，不需要额外的离子注入工艺来弥补由间隔物引起的较低编程效率。 此外，消除了在用于形成间隔物的蚀刻回加工过程中产生的对场氧化物的损伤引起的漏电流。

公开(公告)号：US5920499A

公开(公告)日：1999-07-06

申请号：US969151

申请日：1997-11-12

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： G11C17/06

CPC分类号： G11C17/06

摘要： A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative high voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

摘要翻译： 二极管型只读存储器（ROM）包括二极管作为存储单元。 二极管是逻辑电平“on”存储器单元，并且耦合到ROM中的一个字线和一个位线。 给予耦合到二极管的位线的相对高电压，并且相应的高电压被给予相应的字线。 因此，可以读出保存在二极管中的数据。

公开(公告)号：US5891777A

公开(公告)日：1999-04-06

申请号：US808258

申请日：1997-02-28

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/8246

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91

摘要： A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The P-type substrate is doped using first N-type ions to form a plurality of essentially parallel N-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the N-pole regions. The P-type substrate is doped and annealed, to form a plurality of N-type diffusion regions under the exposed portions of the N-pole regions. The N-pole regions are doped and annealed, to form a plurality of P-type diffusion regions in the exposed portions of the N-pole regions. A metal layer is formed which fills the contact windows. The metal layer is patterned to form a plurality of essentially parallel word lines. A read only memory device is proposed that includes a plurality of essentially parallel N-pole regions are located on a substrate. A plurality of N-type diffusion regions are located under selected portions of respective N-pole regions. A plurality of P-type diffusion regions are located over respective selected portions of the N-pole regions. Each respective P-type diffusion region and associated N-pole region forms a diode.

摘要翻译： 形成ROM的方法包括在P型衬底上形成衬垫氧化层，在衬垫氧化层上形成氮化硅层并对氮化硅层进行构图。 在衬底上形成场氧化物层。 去除氮化硅层。 使用第一N型离子掺杂P型衬底，以形成多个基本上平行的N极区域。 在场氧化物层上形成绝缘层。 在绝缘层内形成多个接触窗以暴露N极区域的一部分。 P型衬底被掺杂和退火，以在N极区域的暴露部分之下形成多个N型扩散区域。 N极区域被掺杂并退火，以在N极区域的露出部分中形成多个P型扩散区域。 形成填充接触窗的金属层。 将金属层图案化以形成多个基本平行的字线。 提出了一种只读存储器件，其包括位于衬底上的多个基本平行的N极区域。 多个N型扩散区域位于各个N极区域的选定部分的下方。 多个P型扩散区域位于N极区域的各个选定部分上。 每个相应的P型扩散区和相关的N极区形成二极管。

公开(公告)号：US5610088A

公开(公告)日：1997-03-11

申请号：US405321

申请日：1995-03-16

申请人： Kuang-Yeh Chang ,  Yowjuang W. Liu

发明人： Kuang-Yeh Chang ,  Yowjuang W. Liu

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823814 ,  Y02P80/30

摘要： A method of fabricating an FET or CMOS transistor that includes lightly doped drain ("LDD") regions which minimizes oxide loss while requiring a lesser number of masks. Consequently, manufacturing cost, cycle times and yield loss can be minimized. In one aspect, the present invention provides a method of fabricating an FET having a LDD region using only one mask, comprising the sequential steps of (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a barrier material layer over said substrate including said gate; (d) forming an oxide layer over said barrier material layer; (e) selectively etching said oxide layer with respect to said barrier material layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

摘要翻译： 一种制造FET或CMOS晶体管的方法，其包括轻掺杂漏极（“LDD”）区域，其最小化氧化物损耗，同时需要较少数量的掩模。 因此，制造成本，循环时间和产量损失可以最小化。 一方面，本发明提供了一种使用仅一个掩模制造具有LDD区域的FET的方法，包括以下顺序步骤：（a）提供具有由场氧化物区域限定的有源区的衬底; （b）提供具有侧边缘的覆盖所述有源区的一部分的栅极; （c）在包括所述栅极的所述衬底上形成阻挡材料层; （d）在所述阻挡材料层上形成氧化物层; （e）相对于所述阻挡材料层选择性地蚀刻所述氧化物层，以围绕所述栅极的侧边缘形成氧化物侧壁; （f）使用所述氧化物侧壁间隔物作为掩模，在所述栅极的侧边缘周围注入重掺杂的源极和漏极区域; （g）去除所述氧化物侧壁间隔物; 以及（h）在所述重掺杂漏极区附近围绕所述栅极的一个侧边缘注入轻掺杂漏极区。

公开(公告)号：US5587332A

公开(公告)日：1996-12-24

申请号：US938727

申请日：1992-09-01

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

摘要翻译： 本发明涉及使用多晶硅 - 多晶硅热电子发射来擦除单元的存储器内容的快闪EEPROM单元。 示例性实施例包括侧栅极，控制栅极，浮置栅极和源极和漏极区域。 这些栅极和源极和漏极区域的适当偏置控制浮栅的电子群。 存储单元可以是双重多晶硅或三重多晶硅品种。 外围晶体管由最后形成的多晶硅层形成，以避免外围晶体管的劣化。

公开(公告)号：US5290734A

公开(公告)日：1994-03-01

申请号：US736162

申请日：1991-07-26

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的衬底上的氧化物层，设置在开口内并接触衬底的非晶硅材料，设置在非晶态上的导电保护材料，例如钛钨 硅材料和衬在保护材料内形成的凹部的壁上的氧化物间隔物。 保护材料和间隔物为反熔丝结构提供更严格的编程电压分布，并有助于防止反熔丝故障。

公开(公告)号：US5198381A

公开(公告)日：1993-03-30

申请号：US758554

申请日：1991-09-12

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

摘要翻译： 本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。 隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。 隧道区域包括通过两个植入阶段制造的隧道门。 因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。 此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。 定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

公开(公告)号：US20090029541A1

公开(公告)日：2009-01-29

申请号：US12211608

申请日：2008-09-16

申请人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

发明人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

IPC分类号： H01L21/44

CPC分类号： H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer.

摘要翻译： 制造抗熔丝的方法包括首先在具有第一导电类型的衬底上形成电介质层。 接下来，在电介质层上形成导电层。 然后执行第一离子注入工艺，使得导电层具有第一导电类型。 此后，对导电层和电介质层进行构图以形成栅极和栅极电介质层。 栅极和栅极电介质层一起构成栅极结构。 最后，具有第二导电类型的两个源极/漏极区域形成在栅极的相应侧的衬底中。 此外，编制反熔丝的方法包括首先向栅极施加电压以分解栅极电介质层。 然后对栅极和衬底进行电导或在栅极电介质层击穿之后在P / N结中形成P / N正向偏压。