公开(公告)号：US20190265293A1

公开(公告)日：2019-08-29

申请号：US15903231

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield ,  Eric Hunt-Schroeder ,  Mark D. Jacunski

IPC: G01R31/26 ,  G01R31/28

Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

公开(公告)号：US10382049B1

公开(公告)日：2019-08-13

申请号：US16122993

申请日：2018-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric Hunt-Schroeder ,  John A. Fifield

IPC: H03M1/10 ,  G01R35/00 ,  H03M1/66 ,  H03M1/06

Abstract: Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

公开(公告)号：US10192590B1

公开(公告)日：2019-01-29

申请号：US15788289

申请日：2017-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield ,  Eric Hunt-Schroeder

IPC: G11C5/14 ,  G05F1/595 ,  G05F1/10 ,  H03K17/16

Abstract: Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.

公开(公告)号：US20190165669A1

公开(公告)日：2019-05-30

申请号：US15822318

申请日：2017-11-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric Hunt-Schroeder ,  John A. Fifield ,  Dale E. Pontius

IPC: H02M1/36 ,  H02M3/07 ,  G05F3/20

Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.

公开(公告)号：US10163526B2

公开(公告)日：2018-12-25

申请号：US15920677

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield ,  Eric D. Hunt-Schroeder ,  Darren L. Anand

IPC: G11C17/00 ,  G11C29/00 ,  G11C17/18 ,  G11C17/16 ,  G11C29/50

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

公开(公告)号：US09837168B1

公开(公告)日：2017-12-05

申请号：US15266201

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield ,  Eric D. Hunt-Schroeder

IPC: G11C17/00 ,  G11C17/18

CPC classification number: G11C17/18 ,  G11C5/147 ,  G11C8/08

Abstract: The present disclosure relates to a method of generating a high differential read current through a non-volatile memory, including receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC), and generating the high differential read current through a difference between the first current and the second current.