公开(公告)号：US20160064250A1

公开(公告)日：2016-03-03

申请号：US14931277

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Jody Fronheiser ,  Witold P. Maszara

IPC: H01L21/3205 ,  H01L21/3105

CPC classification number: H01L21/32055 ,  H01L21/3105 ,  H01L21/76224 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66765 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a metastable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height. In another case, a metastable replacement fin is grown to a height that is greater than an unconfined metastable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height.

Abstract translation: 本文公开了用于形成处于稳定或亚稳态的替代翅片材料的各种方法。 在一种情况下，亚稳态替代翅片生长到大于置换翅片材料的无约束稳定的临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。 在另一种情况下，亚稳替代鳍生长到高于替代翅片材料的无约束亚稳临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。

公开(公告)号：US20150028348A1

公开(公告)日：2015-01-29

申请号：US13948374

申请日：2013-07-23

Applicant: Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（finFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 和嵌入式S / D的外延（epi）底部区域，外延底部区域计数器掺杂到嵌入式S / D的极性。 该器件还包括一组注入在epi底部区域下方的注入区域，其中该组注入区域可以是掺杂的，而epi底部区域未被掺杂。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

公开(公告)号：US20150024573A1

公开(公告)日：2015-01-22

申请号：US13944200

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Jody Fronheiser ,  Witold P. Maszara

IPC: H01L21/762

CPC classification number: H01L21/32055 ,  H01L21/3105 ,  H01L21/76224 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66765 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a stable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 104 defects/cm2 or less throughout its entire height. In another case, a metastable replacement fin is grown to a height that is greater than an unconfined metastable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height.

Abstract translation: 本文公开了用于形成处于稳定或亚稳态的替代翅片材料的各种方法。 在一种情况下，稳定的替换翅片生长到比替换翅片材料的无约束的稳定的临界厚度大的高度，并且其整个高度的缺陷密度为104个缺陷/ cm2或更小。 在另一种情况下，亚稳替代鳍生长到高于替代翅片材料的无约束亚稳临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。

公开(公告)号：US20150001591A1

公开(公告)日：2015-01-01

申请号：US13927698

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

IPC: H01L29/78 ,  H01L21/265

CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Abstract translation: 公开了具有部分电介质隔离的散装finFET。 电介质隔离设置在通道下方，并且基本上由通道限定，使得其不横向延伸超过源极和漏极区下方的沟道。 这允许增加与沟道相邻放置的SiGe源极和漏极应力器体积，从而允许更加紧张的通道，这改善了载流子迁移率。 N +掺杂的硅区域设置在电介质隔离的下方，并横向延伸超过沟道并且在应力源和漏极区之下，与P +掺杂的源极和漏极SiGe应力器形成反向偏置的p / n结，以使来自下面的漏电流最小化 绝缘体。