公开(公告)号：US09276118B2

公开(公告)日：2016-03-01

申请号：US14640851

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个鳍片，在鳍片的部分上形成多个栅极区域，其中栅极区域彼此间隔开，形成间隔物 在每个相应的栅极区域上，在每个鳍片上外延生长第一外延区域，在相邻鳍片之间的第一外延区域合并之前停止第一外延区域的生长，在包括鳍片的衬底上形成介电层，并且第一外延 在相邻栅极区之间的一个或多个部分处从所述鳍片去除所述电介质层和所述第一外延区域，以形成一个或多个接触区域沟槽，以及在所述一个或多个接触区域中的所述鳍片上外延生长第二外延区域 沟槽，其中相邻鳍片上的第二外延区域彼此合并。

公开(公告)号：US20180190797A1

公开(公告)日：2018-07-05

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/324 ,  H01L21/321 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09548356B2

公开(公告)日：2017-01-17

申请号：US14714779

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US09530860B2

公开(公告)日：2016-12-27

申请号：US14578768

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.

Abstract translation: 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。

公开(公告)号：US09391091B2

公开(公告)日：2016-07-12

申请号：US14696693

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L21/425 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

Abstract: An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.