公开(公告)号：US09508640B2

公开(公告)日：2016-11-29

申请号：US13940874

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Szu-Lin Cheng ,  Keith E. Fogel ,  Edward W. Kiewra ,  Amlan Majumdar ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/485 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823878 ,  H01L23/485 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract translation: 用于形成具有多层接触结构的器件的方法包括将通孔中的第一触点形成为第一级，在第一触点的暴露部分上形成电介质覆盖层，并在覆盖层上形成电介质层。 通孔在电介质层中向下开到封盖层。 孔通过通孔在封盖层中打开以露出第一触点。 接触连接器和第二触点形成在通孔中，使得第一和第二触点通过接触连接器通过覆盖层连接以形成多层接触。

公开(公告)号：US09431494B2

公开(公告)日：2016-08-30

申请号：US14739137

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L21/283 ,  H01L29/10 ,  H01L29/201 ,  H01L29/417

CPC classification number: H01L29/42356 ,  H01L21/28026 ,  H01L21/283 ,  H01L29/1054 ,  H01L29/201 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

公开(公告)号：US09711648B1

公开(公告)日：2017-07-18

申请号：US15232164

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Effendi Leobandung ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66522 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.

公开(公告)号：US09224866B2

公开(公告)日：2015-12-29

申请号：US14010589

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract translation: 在基板上形成包括第二半导体材料和第一半导体材料的从底部到顶部的垂直叠层的半导体鳍片。 形成跨越半导体鳍片的一次性栅极结构。 使用一次性栅极结构作为注入掩模形成源区和漏区，可以形成至少一个半导体外壳层或半导体盖层作为蚀刻停止结构。 随后形成平坦化介电层。 通过去除一次性栅极结构形成栅极腔。 第二半导体材料的一部分被选择性地移除到栅极腔内的第一半导体材料，使得半导体鳍片的中间部分悬浮在衬底上。 依次形成栅介质层和栅电极。 栅电极横向围绕鳍场效应晶体管的体区。

公开(公告)号：US09666684B2

公开(公告)日：2017-05-30

申请号：US13945281

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/7784 ,  H01L29/78

Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.

公开(公告)号：US09530860B2

公开(公告)日：2016-12-27

申请号：US14578768

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.

Abstract translation: 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。

公开(公告)号：US20160099329A1

公开(公告)日：2016-04-07

申请号：US14968061

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L21/31 ,  H01L21/306 ,  H01L21/768 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.