公开(公告)号：US09660030B2

公开(公告)日：2017-05-23

申请号：US14473033

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shom Ponoth ,  Marc A. Bergendahl ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC: H01L29/165 ,  H01L21/338 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

公开(公告)号：US09263290B2

公开(公告)日：2016-02-16

申请号：US14843085

申请日：2015-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

公开(公告)号：US09245965B2

公开(公告)日：2016-01-26

申请号：US14327598

申请日：2014-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/088 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.

Abstract translation: 包括从半导体衬底蚀刻的第一多个散热片和第二多个散热片的结构以及位于半导体衬底上方以及第一组散热片和第二组散热片之间的填充材料，填充材料不接触 第一多个翅片或第二多个翅片。

公开(公告)号：US20150270262A1

公开(公告)日：2015-09-24

申请号：US14731569

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L27/088 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

Abstract translation: 本文公开的一种方法包括分别在第一和第二间隔开的栅电极结构的每个相对的间隔开的第一和第二端面表面的整个开口中的开口中形成线端保护层，以及 形成邻近每个栅极电极结构的相对侧壁表面的侧壁间隔件，但不邻近具有定位在其上的线端保护层的相对的第一和第二端面表面。

公开(公告)号：US08941156B2

公开(公告)日：2015-01-27

申请号：US13735315

申请日：2013-01-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US08835244B2

公开(公告)日：2014-09-16

申请号：US13773397

申请日：2013-02-21

Applicant: GlobalFoundries, Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Chanro Park ,  Shom Ponoth

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/66477 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/788

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

公开(公告)号：US09379135B2

公开(公告)日：2016-06-28

申请号：US14723681

申请日：2015-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/76205 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

公开(公告)号：US20160118385A1

公开(公告)日：2016-04-28

申请号：US14981574

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure, wherein an internal sidewall surface of each of the spaced-apart sidewall spacers has a stepped cross-sectional configuration

Abstract translation: 晶体管器件包括位于半导体衬底上方的栅极结构和位于衬底上方的间隔开的侧壁隔离物和栅极结构的相邻侧壁，其中每个间隔开的侧壁间隔件的内侧壁表面具有阶梯状横截面 组态

公开(公告)号：US09269629B2

公开(公告)日：2016-02-23

申请号：US14528830

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/78

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

公开(公告)号：US09269621B2

公开(公告)日：2016-02-23

申请号：US14449314

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract translation: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。