公开(公告)号：US09852954B2

公开(公告)日：2017-12-26

申请号：US14882640

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

公开(公告)号：US20170294522A1

公开(公告)日：2017-10-12

申请号：US15092168

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Muhammad Rahman ,  Srikanth Balaji Samavedam

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/306 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity comprises an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity

公开(公告)号：US20140367787A1

公开(公告)日：2014-12-18

申请号：US13918536

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

Abstract translation: 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

公开(公告)号：US20210036108A1

公开(公告)日：2021-02-04

申请号：US16526529

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Srikanth Balaji Samavedam

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.

公开(公告)号：US10347748B2

公开(公告)日：2019-07-09

申请号：US15092168

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Muhammad Rahman ,  Srikanth Balaji Samavedam

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/08 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

公开(公告)号：US20180047641A1

公开(公告)日：2018-02-15

申请号：US15792357

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

公开(公告)号：US09455201B2

公开(公告)日：2016-09-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam ,  Bongki Lee ,  Jin Ping Liu

IPC: H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。