公开(公告)号：US09698269B2

公开(公告)日：2017-07-04

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L21/321 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US09455201B2

公开(公告)日：2016-09-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam ,  Bongki Lee ,  Jin Ping Liu

IPC: H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09373535B2

公开(公告)日：2016-06-21

申请号：US14515628

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L21/62 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract translation: 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US09263520B2

公开(公告)日：2016-02-16

申请号：US14050494

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping Liu ,  Jing Wan ,  Andy Wei

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract translation: 提出了用于促进半导体器件的制造的方法，例如栅极全能纳米线场效应晶体管。 所述方法包括例如：提供至少一个堆叠结构，其包括在衬底结构上方延伸的至少一个层或凸块; 选择性地氧化所述至少一个堆叠结构的至少一部分以形成至少一个纳米线，所述至少一个纳米线在由所述堆叠结构的氧化材料包围的所述堆叠结构内延伸; 以及从所述堆叠结构中去除所述氧化的材料，暴露所述纳米线。 这种选择性氧化可以包括氧化衬底结构的上部，例如支撑堆叠结构的一个或多个翅片的上部，以促进纳米线的完全360度曝光。 在一个实施例中，堆叠结构包括一个或多个菱形凸块或凸脊。

公开(公告)号：US20150069515A1

公开(公告)日：2015-03-12

申请号：US14023558

申请日：2013-09-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Jin Ping Liu ,  Jill Hildreth ,  Taejoon Han

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖半导体衬底的翅片结构。 翅片结构限定了在垂直于横向方向的纵向方向上延伸的翅片轴线，并且具有平行于翅片轴线的两个翅片侧壁。 该方法包括形成覆盖翅片结构并横向于翅片轴线的栅极结构。 此外，该方法包括在翅片结构上生长外延材料并限制外延材料在横向上的生长。

公开(公告)号：US09620380B1

公开(公告)日：2017-04-11

申请号：US14972804

申请日：2015-12-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Jin Ping Liu ,  Jiong Li

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/108

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/10826 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

公开(公告)号：US09472465B2

公开(公告)日：2016-10-18

申请号：US14270824

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/32133 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66477

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，提供了一种用于制造集成电路的方法。 该方法包括在半导体衬底上的层间电介质材料的第二FET区域中的第一FET区域和第二FET沟槽中形成第一FET沟槽，至少部分地用功函数金属填充第一和第二FET沟槽以形成 功函数金属层，并且至少部分去除第二FET沟槽中的功函数金属层的一部分。 第一FET沟槽被定义为NFET沟槽，并且第二FET沟槽被定义为PFET沟槽。

公开(公告)号：US09466723B1

公开(公告)日：2016-10-11

申请号：US14751718

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Qiang Fang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/283 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.

Abstract translation: 一种方法包括在半导体材料之上形成占位符源极/漏极接触结构。 执行保形沉积工艺以在占位符接触结构之上形成衬垫层。 在衬层上方形成介电层。 执行第一平面化处理以去除电介质层的材料并将衬垫层的第一顶表面暴露在占位符接触结构之上。 在电介质层上方形成第一盖层。 执行第二平面化处理以去除第一盖层和衬垫层的材料以暴露占位符接触结构的第二顶表面。 去除占位符接触结构以在电介质层中限定源极/漏极接触凹部。 源极/漏极接触凹部中的电介质层的侧壁被衬里层覆盖。 导电材料形成在接触凹部中。

公开(公告)号：US09343371B1

公开(公告)日：2016-05-17

申请号：US14725552

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66803

Abstract: Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

Abstract translation: 提供了用于制造翅片结构的方法。 所述方法包括：制造至少一个翅片结构，所述至少一个翅片结构具有将上部与下部分隔开的掺杂中间部分，并且所述制造包括：提供与所述至少下部的下部接触的隔离层 一个鳍结构; 在所述隔离层上方形成掺杂层并与所述至少一个翅片结构接触; 以及退火所述掺杂层以将掺杂剂从其中扩散到所述至少一个鳍结构中以形成其掺杂的中间部分，其中所述隔离层抑制掺杂剂从所述掺杂层扩散到所述至少一个鳍结构的下部。

公开(公告)号：US09312145B2

公开(公告)日：2016-04-12

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L21/469 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。