公开(公告)号：US09576952B2

公开(公告)日：2017-02-21

申请号：US14188778

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Manfred Eller ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract translation: 提供集成电路和制造方法。 集成电路包括：设置在衬底结构上的变化的栅极结构，所述变化的栅极结构包括在衬底结构的第一区域中的第一栅极堆叠，以及在衬底结构的第二区域中的第二栅极堆叠; 所述第一区域中的第一场效应晶体管，所述第一场效应晶体管包括所述第一栅极叠层并具有第一阈值电压; 以及第二区域中的第二场效应晶体管，所述第二场效应晶体管包括所述第二栅极堆叠并且具有第二阈值电压，其中所述第一阈值电压不同于所述第二阈值电压。 所述方法包括提供变化的栅极结构，所述提供包括：具有不同厚度（es）的不同栅极结构的尺寸层。

公开(公告)号：US20200066883A1

公开(公告)日：2020-02-27

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US09362180B2

公开(公告)日：2016-06-07

申请号：US14189085

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract translation: 在一个方面，这里提出了具有第一多个场效应晶体管和第二多个场效应晶体管的集成电路，其中第一多个场效应晶体管的场效应晶体管各自具有第一栅极堆叠，并且其中场效应 第二多个场效应晶体管的晶体管每个都具有第二栅极堆叠，第二栅极堆叠通过具有与第一栅极堆叠共同的金属层与第一栅极堆叠而不同于第一栅极堆叠，第二栅极堆叠包括第一栅极堆叠的第一厚度 第一栅极堆叠和第二栅极堆叠处的第二厚度。

公开(公告)号：US09082698B1

公开(公告)日：2015-07-14

申请号：US14201122

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Johannes Marinus van Meer ,  Manfred Eller

IPC: H01L21/425 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L29/1083 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a fin in a substrate, forming a well implant region in at least the substrate, forming a punch-stop implant region in the fin, performing at least one neutral implantation process with at least one neutral implant material to form a neutral boron-diffusion-blocking implant region in the fin, wherein an upper surface of the neutral boron-diffusion-blocking implant region is positioned closer to an upper surface of the fin than either the punch-stop implant region or the well implant region and, after forming the well implant region, the punch-stop implant region and the neutral boron-diffusion-blocking implant region, forming a gate structure above the fin.

Abstract translation: 所公开的一种示例性方法包括在衬底中形成翅片，在至少衬底中形成井注入区域，在翅片中形成冲压停止注入区域，至少执行至少一个中性注入工艺 中性植入材料以在翅片中形成中性硼扩散阻挡植入区域，其中中性硼扩散阻挡注入区域的上表面被定位成更接近翅片的上表面，比穿孔止动植入区域 或井注入区域，并且在形成阱注入区域之后，形成穿孔停止注入区域和中性硼扩散阻挡注入区域，在鳍片上方形成栅极结构。

公开(公告)号：US10553707B1

公开(公告)日：2020-02-04

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US09455201B2

公开(公告)日：2016-09-27

申请号：US14188898

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manoj Joshi ,  Manfred Eller ,  Rohit Pal ,  Richard J. Carter ,  Srikanth Balaji Samavedam ,  Bongki Lee ,  Jin Ping Liu

IPC: H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管和形成在衬底结构中的第二场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一衬底结构掺杂，第一栅叠层和第一阈值电压。 第二场效应晶体管可以包括第一衬底结构掺杂，不同于第一栅极叠层的第二栅极堆叠以及不同于第一阈值电压的第二阈值电压。