公开(公告)号：US10170614B2

公开(公告)日：2019-01-01

申请号：US15971419

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/45 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10

Abstract: A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.

公开(公告)号：US20180198000A1

公开(公告)日：2018-07-12

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US09960284B2

公开(公告)日：2018-05-01

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L29/161

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US20170317209A1

公开(公告)日：2017-11-02

申请号：US15198038

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped with dopants of a first conductivity type and the second well being doped with dopants of a second conductivity type, a third well within the first well, a gate structure partially formed over the first and second wells, and a first epi region on the third well and a drain region electrically coupled to the second well, the first epi region being doped with dopants of the second conductivity type.

公开(公告)号：US09515155B2

公开(公告)日：2016-12-06

申请号：US14136815

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62 ,  H01L23/525

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。