公开(公告)号：US20170125610A1

公开(公告)日：2017-05-04

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/49 ,  H01L27/06 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US20150179632A1

公开(公告)日：2015-06-25

申请号：US14136581

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/525

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：在隔离区域上形成电可编程熔丝（e-fuse）和在晶片的有源区上形成晶体管，其中形成晶体管包括在衬底上形成虚拟栅极，去除 虚拟栅极和形成金属栅极代替虚拟栅极，并且形成e熔丝包括在隔离区域上方形成含金属层，在形成虚拟栅极的过程中在含金属层上形成半导体层 栅极和与虚拟栅极相同的材料，在形成在含金属层上的半导体层上形成硬掩模层，并且在去除虚拟栅极的过程中在硬掩模层和半导体层中形成接触开口。

公开(公告)号：US09012313B2

公开(公告)日：2015-04-21

申请号：US14173995

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu

IPC: H01L21/425 ,  H01L21/20 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L29/8605 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  Y10S438/914

Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.

Abstract translation: 半导体结构包括衬底和设置在衬底上的电阻器。 电阻器包括第一材料层，第二材料层，第一接触结构和第二接触结构。 第一材料层包括金属和金属化合物中的至少一种。 第二材料层包括半导体材料。 第二材料层设置在第一材料层上并且包括第一子层和第二子层。 第二子层设置在第一子层上。 第一子层和第二子层是不同的掺杂的。 第一接触结构和第二接触结构中的每一个提供到第二材料层的第二子层的电连接。

公开(公告)号：US10886419B2

公开(公告)日：2021-01-05

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US09530770B2

公开(公告)日：2016-12-27

申请号：US14261021

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Alexandru Romanescu ,  Gerd Zschätzsch ,  Christian Schippel

IPC: H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/78

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract translation: 提供了具有由栅极金属形成的电阻结构的集成电路及其制造方法。 在一个实施例中，制造集成电路的方法包括：提供具有电阻区域和晶体管区域的半导体衬底。 该方法在电阻器区域和半导体衬底的晶体管区域上沉积栅极金属，并且栅极金属在电阻器区域中形成栅极金属层。 该方法包括蚀刻栅极金属以从电阻器区域中的栅极金属层形成电阻器结构。 此外，该方法包括在电阻器区域中形成与电阻器结构的接触。

公开(公告)号：US09524962B2

公开(公告)日：2016-12-20

申请号：US14136581

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L29/49 ,  H01L23/62 ,  H01L21/285 ,  H01L27/06 ,  H01L23/525 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：在隔离区域上形成电可编程熔丝（e-fuse）和在晶片的有源区上形成晶体管，其中形成晶体管包括在衬底上形成虚拟栅极，去除 虚拟栅极和形成金属栅极代替虚拟栅极，并且形成e熔丝包括在隔离区域上方形成含金属层，在形成虚拟栅极的过程中在含金属层上形成半导体层 栅极和与虚拟栅极相同的材料，在形成在含金属层上的半导体层上形成硬掩模层，并且在去除虚拟栅极的过程中在硬掩模层和半导体层中形成接触开口。

公开(公告)号：US20180198000A1

公开(公告)日：2018-07-12

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US09960284B2

公开(公告)日：2018-05-01

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L29/161

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US20160204065A1

公开(公告)日：2016-07-14

申请号：US15077378

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Mikalo ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L23/345 ,  H01L23/62 ,  H01L27/1026 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.

公开(公告)号：US20140264342A1

公开(公告)日：2014-09-18

申请号：US14173995

申请日：2014-02-06

Applicant: Globalfoundries Inc.

Inventor： Alexandru Romanescu

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L29/8605 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  Y10S438/914

Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.

Abstract translation: 半导体结构包括衬底和设置在衬底上的电阻器。 电阻器包括第一材料层，第二材料层，第一接触结构和第二接触结构。 第一材料层包括金属和金属化合物中的至少一种。 第二材料层包括半导体材料。 第二材料层设置在第一材料层上并且包括第一子层和第二子层。 第二子层设置在第一子层上。 第一子层和第二子层是不同的掺杂的。 第一接触结构和第二接触结构中的每一个提供到第二材料层的第二子层的电连接。