公开(公告)号：US10360334B2

公开(公告)日：2019-07-23

申请号：US15428449

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

IPC: G06F17/50

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

公开(公告)号：US10340288B2

公开(公告)日：2019-07-02

申请号：US15226867

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L29/78 ,  H01L27/11 ,  H01L27/02

Abstract: At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal configuration in a second metal layer of the memory cell. A third set of metal features are formed in the unidirectional horizontal configuration in a second metal layer of a functional cell for providing routing compatibility between the memory cell and the functional cell. The memory cell is placed adjacent to the functional cell for forming an integrated circuit device.

公开(公告)号：US10333497B1

公开(公告)日：2019-06-25

申请号：US15944813

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Mahbub Rashed ,  Sushama Davar ,  Navneet Jain

IPC: H03K3/011 ,  G06F13/10 ,  H03K5/24

Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

公开(公告)号：US10303196B1

公开(公告)日：2019-05-28

申请号：US15966300

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Arif A. Siddiqi ,  Mahbub Rashed

IPC: G05F3/20 ,  G11C5/14 ,  H03K19/00 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092

Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.

公开(公告)号：US10096595B2

公开(公告)日：2018-10-09

申请号：US15286196

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain ,  Anurag Mittal ,  Sangmoon Kim

IPC: H01L27/02 ,  H01L27/06 ,  G06F17/50 ,  H01L27/11 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

公开(公告)号：US20180225406A1

公开(公告)日：2018-08-09

申请号：US15428449

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

公开(公告)号：US09142513B2

公开(公告)日：2015-09-22

申请号：US14645598

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook K E ,  Roderick Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/538 ,  H01L29/78 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

公开(公告)号：US10658294B2

公开(公告)日：2020-05-19

申请号：US16411237

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L23/50 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

公开(公告)号：US20200117226A1

公开(公告)日：2020-04-16

申请号：US16159831

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arif A. Siddiqi ,  Juhan Kim ,  Mahbub Rashed

IPC: G05F3/20 ,  G11C5/14

Abstract: Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal.

公开(公告)号：US10366954B1

公开(公告)日：2019-07-30

申请号：US15962065

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02 ,  H01L23/50

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.