公开(公告)号：US20220068340A1

公开(公告)日：2022-03-03

申请号：US17007512

申请日：2020-08-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Steven R. Soss

IPC: G11C11/16 ,  G11C7/20 ,  G11C5/06

Abstract: Disclosed are embodiments of a non-volatile static random access memory (NV-SRAM) cell. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. These NVM circuits capture data values stored on the data nodes of the SRAM circuit prior to power down and rewrite those data values back onto the data nodes of the SRAM circuit upon power up. Also disclosed are embodiments of a method of operating a selected NV-SRAM cell in a memory array.

公开(公告)号：US20210134881A1

公开(公告)日：2021-05-06

申请号：US16668092

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul

IPC: H01L27/22 ,  H01L23/528 ,  H01L23/522

Abstract: One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

公开(公告)号：US12002869B2

公开(公告)日：2024-06-04

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/783

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11735257B2

公开(公告)日：2023-08-22

申请号：US17380093

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nishtha Gaul ,  Bipul C. Paul ,  Akhilesh R. Jaiswal

IPC: G11C7/12 ,  G11C13/00 ,  H03K19/017 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/161 ,  G11C11/1673 ,  H03K19/01721 ,  G11C11/1659 ,  G11C2213/79

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

公开(公告)号：US11587601B1

公开(公告)日：2023-02-21

申请号：US17445461

申请日：2021-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Shashank S. Nemawarkar

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

公开(公告)号：US20230027460A1

公开(公告)日：2023-01-26

申请号：US17380093

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nishtha Gaul ,  Bipul C. Paul ,  Akhilesh R. Jaiswal

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

公开(公告)号：US20220416054A1

公开(公告)日：2022-12-29

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L27/092

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11475941B2

公开(公告)日：2022-10-18

申请号：US17110674

申请日：2020-12-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. Jaiswal ,  Bipul C. Paul ,  Steven R. Soss

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

公开(公告)号：US11469309B2

公开(公告)日：2022-10-11

申请号：US16804264

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US20210159273A1

公开(公告)日：2021-05-27

申请号：US16691694

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joe A. Versaggi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.