公开(公告)号：US20240125732A1

公开(公告)日：2024-04-18

申请号：US18047405

申请日：2022-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Mark D. Levy ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: G01N27/414

CPC classification number: G01N27/414

Abstract: A structure includes a cavity in a semiconductor substrate; a field effect transistor positioned over the cavity; an opening in the semiconductor substrate extending to the cavity; and a layer of insulating material filling the opening and forming an insulating material window to the cavity.

公开(公告)号：US20230352570A1

公开(公告)日：2023-11-02

申请号：US17733118

申请日：2022-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Sarah A. McTaggart ,  Laura J. Silverstein ,  Qizhi Liu ,  Jason E. Stephens

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/732 ,  H01L29/66272 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/456

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.

公开(公告)号：US11581450B2

公开(公告)日：2023-02-14

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/101 ,  H01L31/107 ,  H01L31/18 ,  H01L31/0352

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US20220189818A1

公开(公告)日：2022-06-16

申请号：US17118697

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Fuad H. Al-Amoody ,  Felix P. Anderson ,  Spencer H. Porter ,  Mark D. Levy ,  Siva P. Adusumilli

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417

Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.

公开(公告)号：US12154956B1

公开(公告)日：2024-11-26

申请号：US18632902

申请日：2024-04-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Mark D. Levy ,  John J. Ellis-Monaghan ,  Michael J. Zierak ,  Kristin Marie Welch

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.

公开(公告)号：US20240204090A1

公开(公告)日：2024-06-20

申请号：US18065674

申请日：2022-12-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Mark D. Levy

IPC: H01L29/778 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/32139 ,  H01L29/0642 ,  H01L29/0891 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/66462

Abstract: A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer with a thick portion positioned laterally between thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between thin portions. The gate also includes a gate conductor layer on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.

公开(公告)号：US20230223337A1

公开(公告)日：2023-07-13

申请号：US17572681

申请日：2022-01-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Fuad H. Al-Amoody ,  Siva P. Adusumilli ,  Spencer H. Porter ,  Ephrem Gebreselasie ,  Rajendran Krishnasamy

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/36 ,  H01L23/34 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76877 ,  H01L23/36 ,  H01L23/345 ,  H01L21/76832 ,  H01L23/5226 ,  H01L21/76816

Abstract: A semiconductor structure includes a semiconductor device (e.g., an e-fuse or photonic device) and a metallic heating element adjacent thereto. The heating element has a lower portion within a middle of the line (MOL) dielectric layer adjacent to the semiconductor device and an upper portion with a tapered top end that extends into a back end of the line (BEOL) dielectric layer. A method of forming the semiconductor structure includes forming a cavity such that it has both a lower section, which extends from a top surface of a MOL dielectric layer downward toward a semiconductor device, and an upper section, which extends from the top surface of the MOL dielectric layer upward and which is capped by an area of a BEOL dielectric layer having a concave bottom surface. A metallic fill material can then be deposited into the cavity (e.g., through via openings) to form the heating element.

公开(公告)号：US11646351B2

公开(公告)日：2023-05-09

申请号：US17146513

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/49 ,  H01L29/47 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11611002B2

公开(公告)日：2023-03-21

申请号：US16935854

申请日：2020-07-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Edward W. Kiewra ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan

IPC: H01L29/868 ,  H01L31/107 ,  H01L29/66 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: a spiral fin structure comprising semiconductor substrate material and dielectric material; a photosensitive semiconductor material over sidewalls and a top surface of the spiral fin structure, the photosensitive semiconductor material positioned to capture laterally emitted incident light; a doped semiconductor material above the photosensitive semiconductor material; and contacts electrically contacting the semiconductor substrate material and the doped semiconductor material from a top surface thereof.

公开(公告)号：US11605649B2

公开(公告)日：2023-03-14

申请号：US17306078

申请日：2021-05-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Alvin J. Joseph ,  Ramsey Hazbun

IPC: H01L27/12 ,  H01L21/762 ,  H01L23/66 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.