公开(公告)号：US20240094465A1

公开(公告)日：2024-03-21

申请号：US17932868

申请日：2022-09-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Mark D. Levy ,  Siva P. Adusumilli ,  Karen A. Nummy ,  Zhuojie Wu ,  Ramsey Hazbun

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13

Abstract: The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. Each of a plurality of optical guard elements are composed of a light absorbing material and are in proximity to the photonic component. The optical guard elements may mimic an outer periphery of at least a portion of the photonic component. The optical guard elements may include at least one of: a germanium body positioned at least partially in a silicon element, a silicon body having a high dopant concentration, and a polysilicon body having a high dopant concentration over the silicon body.

公开(公告)号：US11881506B2

公开(公告)日：2024-01-23

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L29/66431 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US20230417695A1

公开(公告)日：2023-12-28

申请号：US17808176

申请日：2022-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

IPC: G01N27/06 ,  H01L31/105 ,  H01L31/0352 ,  H01L31/18

CPC classification number: G01N27/06 ,  H01L31/105 ,  H01L31/035209 ,  H01L31/1804

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

公开(公告)号：US11502214B2

公开(公告)日：2022-11-15

申请号：US17196756

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Yusheng Bian

IPC: H01L31/105 ,  H01L31/18 ,  H01L31/0352 ,  H01L27/146

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors used with a broadband signal and methods of manufacture. The structure includes: a first photodetector; a second photodetector adjacent to the first photodetector; a first airgap of a first size under the first photodetector structured to detect a first wavelength of light; and a second airgap of a second size under the second photodetector structured to detect a second wavelength of light.

公开(公告)号：US20220189821A1

公开(公告)日：2022-06-16

申请号：US17123184

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Alvin J. Joseph

IPC: H01L21/762 ,  H01L21/763 ,  H01L23/367 ,  H01L27/12

Abstract: A structure includes an active device over an area of a substrate, and a heat spreading isolation structure adjacent the active device. The isolation structure includes a dielectric layer above a heat-conducting layer. The heat-conducting layer may include polycrystalline graphite. The heat-conducting layer provides a heat sink, which provides a high thermal conductivity path for heat with low electrical conductivity. The heat-conducting layer may extend into the substrate. The substrate may include an SOI substrate in which case the heat-conducting layer may extend through the buried insulator thereof.

公开(公告)号：US11282740B2

公开(公告)日：2022-03-22

申请号：US16992165

申请日：2020-08-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy

IPC: H01L21/00 ,  H01L21/763 ,  H01L29/06 ,  H01L29/04

Abstract: Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).

公开(公告)号：US12119383B2

公开(公告)日：2024-10-15

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US12062574B2

公开(公告)日：2024-08-13

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US20240194592A1

公开(公告)日：2024-06-13

申请号：US18064472

申请日：2022-12-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Mark D. Levy ,  Chung Foong Tan

IPC: H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/53271

Abstract: A fuse structure includes a fuse body including a polysilicon, and a metal heater over the fuse body. The fuse structure also includes a heating spreading structure thermally coupled to the metal heater and extending horizontally adjacent to at least one side of the fuse body. The metal heater can be a portion of a metal wire or a resistor including a resistive metal. The heat spreading structure may include a plurality of metal contacts.

公开(公告)号：US11978661B2

公开(公告)日：2024-05-07

申请号：US17118697

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Fuad H. Al-Amoody ,  Felix P. Anderson ,  Spencer H. Porter ,  Mark D. Levy ,  Siva P. Adusumilli

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76865 ,  H01L23/5226 ,  H01L29/41725 ,  H01L23/5283 ,  H01L23/53295

Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.