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    Nanopore-based sequencing chips using stacked wafer technology
    14.
    发明授权
    Nanopore-based sequencing chips using stacked wafer technology 有权

    公开(公告)号：US10006899B2

    公开(公告)日：2018-06-26

    申请号：US14225263

    申请日：2014-03-25

    Applicant: Genia Technologies, Inc.

    Inventor： Hui Tian

    IPC: C12Q1/68 ,  G01N33/487

    CPC classification number: G01N33/48721

    Abstract: A nanopore based sequencing chip is disclosed. The sequencing chip comprises a first portion made from a first wafer. The first portion includes an array of nanopore cells. The first portion further includes a measurement circuit connected to one or more nanopore cells, the measurement circuit producing an output measurement signal. The first portion further includes one or more vias transmitting the output measurement signal. The sequencing chip further includes a second portion made from a second wafer, the second portion comprising one or more corresponding vias receiving the output measurement signal.

    EXPORTING MEASUREMENTS OF NANOPORE ARRAYS
    16.
    发明申请
    EXPORTING MEASUREMENTS OF NANOPORE ARRAYS 审中-公开
    纳米级阵列的出口测量

    公开(公告)号：US20160123923A1

    公开(公告)日：2016-05-05

    申请号：US14534042

    申请日：2014-11-05

    Applicant: Genia Technologies, Inc.

    Inventor： Roger J.A. Chen ,  Hui Tian ,  Santiago Fernandez-Gomez

    IPC: G01N27/447 ,  G01N33/487 ,  C12Q1/68

    CPC classification number: G01N33/48721 ,  B82Y15/00 ,  C12Q1/6869

    Abstract: A method of exporting measurements of a nanopore sensor on a nanopore based sequencing chip is disclosed. An electrical characteristic associated with the nanopore sensor is measured. The electrical characteristic associated with the nanopore sensor is processed. A summary for the electrical characteristic and one or more previous electrical characteristics is determined. The summary for the electrical characteristic and the one or more previous electrical characteristics are exported. Determining the summary includes determining that the electrical characteristic and at least a portion of the one or more previous electrical characteristics correspond to a base call event at the nanopore sensor. The summary represents the electrical characteristic and the at least a portion of the one or more previous electrical characteristics.

    Abstract translation: 公开了一种在基于纳米孔的测序芯片上输出纳米孔传感器测量的方法。 测量与纳米孔传感器相关的电特性。 处理与纳米孔传感器相关的电特性。 确定电特性和一个或多个先前电特性的总结。 导出了电气特性和一个或多个以前的电气特性的总结。 确定总结包括确定电特性和一个或多个先前的电特性的至少一部分对应于纳米孔传感器处的基本呼叫事件。 总结表示电特性和一个或多个先前电特性的至少一部分。

    Process for biosensor well formation
    17.
    发明授权
    Process for biosensor well formation 有权
    生物传感器井形成过程

    公开(公告)号：US09322062B2

    公开(公告)日：2016-04-26

    申请号：US14521427

    申请日：2014-10-22

    Applicant: Genia Technologies, Inc.

    Inventor： Randall W. Davis ,  Edward Shian Liu ,  Eric Takeshi Harada ,  Anne Aguirre ,  Andrew Trans ,  James Pollard ,  Cynthia Cech ,  Hui Tian ,  Robert Yuan ,  John Foster ,  Roger Chen

    IPC: G01N27/327 ,  C12Q1/68 ,  C12M1/34

    CPC classification number: C12Q1/6869 ,  C12M1/34 ,  G01N27/3277 ,  G01N27/3278 ,  G01N27/44791 ,  G01N33/48721 ,  C12Q2565/607 ,  C12Q2565/631

    Abstract: A biochip for molecular detection and sensing is disclosed. The biochip includes a substrate. The biochip includes a plurality of discrete sites formed on the substrate having a density of greater than five hundred wells per square millimeter. Each discrete site includes sidewalls disposed on the substrate to form a well. Each discrete site includes an electrode disposed at the bottom of the well. In some embodiments, the wells are formed such that cross-talk between the wells is reduced. In some embodiments, the electrodes disposed at the bottom of the wells are organized into groups of electrodes, wherein each group of electrodes shares a common counter electrode. In some embodiments, the electrode disposed at the bottom of the well has a dedicated counter electrode. In some embodiments, surfaces of the sidewalls are silanized such that the surfaces facilitate the forming of a membrane in or adjacent to the well.

    Abstract translation: 公开了用于分子检测和感测的生物芯片。 生物芯片包括基底。 生物芯片包括形成在衬底上的多个离散位置，其密度大于每平方毫米500个孔。 每个离散部位包括设置在基底上以形成孔的侧壁。 每个离散位置包括设置在井的底部的电极。 在一些实施例中，形成井，使得井之间的串扰减少。 在一些实施例中，设置在阱的底部的电极被组织成电极组，其中每组电极共享公共对电极。 在一些实施例中，设置在阱底部的电极具有专用的对电极。 在一些实施例中，侧壁的表面被硅烷化，使得表面有助于在孔中或邻近孔的膜的形成。

    NANOPORE-BASED SEQUENCING CHIPS USING STACKED WAFER TECHNOLOGY
    18.
    发明申请
    NANOPORE-BASED SEQUENCING CHIPS USING STACKED WAFER TECHNOLOGY 有权
    基于NANOPORE的测序仪使用堆叠式WAFER技术

    公开(公告)号：US20150275287A1

    公开(公告)日：2015-10-01

    申请号：US14225263

    申请日：2014-03-25

    Applicant: Genia Technologies, Inc.

    Inventor： Hui Tian

    IPC: C12Q1/68

    CPC classification number: G01N33/48721

    Abstract: A nanopore based sequencing chip is disclosed. The sequencing chip comprises a first portion made from a first wafer. The first portion includes an array of nanopore cells. The first portion further includes a measurement circuit connected to one or more nanopore cells, the measurement circuit producing an output measurement signal. The first portion further includes one or more vias transmitting the output measurement signal. The sequencing chip further includes a second portion made from a second wafer, the second portion comprising one or more corresponding vias receiving the output measurement signal.

    Abstract translation: 公开了一种基于纳米孔的测序芯片。 测序芯片包括由第一晶片制成的第一部分。 第一部分包括纳米孔细胞阵列。 第一部分还包括连接到一个或多个纳米孔单元的测量电路，该测量电路产生输出测量信号。 第一部分还包括传输输出测量信号的一个或多个通孔。 排序芯片还包括由第二晶片制成的第二部分，第二部分包括接收输出测量信号的一个或多个对应的通孔。

    Adjustable bilayer capacitance structure for biomedical devices
    20.
    发明授权
    Adjustable bilayer capacitance structure for biomedical devices 有权

    公开(公告)号：US10345290B2

    公开(公告)日：2019-07-09

    申请号：US16021664

    申请日：2018-06-28

    Applicant: Genia Technologies, Inc.

    Inventor： Jennifer Hovis ,  Hui Tian ,  Roger J. A. Chen

    IPC: G01N33/487

    Abstract: A nanopore sequencing device is disclosed. The nanopore sequencing device includes a working electrode. It further includes a dielectric layer, wherein a portion of the dielectric layer is disposed horizontally adjacent to the working electrode and a portion of the dielectric layer is disposed above and covering a portion of the working electrode, and wherein the dielectric layer forms a well having an opening above an uncovered portion of the working electrode. A base surface area of the working electrode is greater than a base surface area of the opening above the uncovered portion of the working electrode.

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