公开(公告)号：US10079208B2

公开(公告)日：2018-09-18

申请号：US15221647

申请日：2016-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Moosung M. Chae

IPC: H01L23/528 ,  H01L29/45 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76883 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0883 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568

Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a conductive region, and an inter-level dielectric (ILD) material positioned on the conductive region, wherein the ILD material includes a contact opening to the conductive region; forming a doped metal layer within the contact opening such that the doped metal layer overlies the conductive region, wherein the doped metal layer includes a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material.

公开(公告)号：US10043753B2

公开(公告)日：2018-08-07

申请号：US15377592

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Zhiguo Sun ,  Joseph F. Shepard, Jr. ,  Moosung M. Chae

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

公开(公告)号：US08932934B2

公开(公告)日：2015-01-13

申请号：US13903283

申请日：2013-05-28

Applicant: GlobalFoundries Inc.

Inventor： Moosung M. Chae ,  Errol Todd Ryan ,  Nicholas Vincent Licausi ,  Christian Witt ,  Ailian Zhao ,  Ming He ,  Sean X. Lin ,  Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/48 ,  H01L21/316 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。