公开(公告)号：US09905460B2

公开(公告)日：2018-02-27

申请号：US14933650

申请日：2015-11-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Moosung M. Chae ,  Ki Young Lee ,  Songkram Srivathanakul

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76858 ,  H01L21/76867 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209

摘要： A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.

公开(公告)号：US20200335435A1

公开(公告)日：2020-10-22

申请号：US16918053

申请日：2020-07-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/525

摘要： Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20180337126A1

公开(公告)日：2018-11-22

申请号：US16049303

申请日：2018-07-30

申请人： GLOBALFOUNDRIES INC.

发明人： Xunyuan Zhang ,  Moosung M. Chae

IPC分类号： H01L23/528 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/40

摘要： Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.

公开(公告)号：US20150255331A1

公开(公告)日：2015-09-10

申请号：US14196842

申请日：2014-03-04

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xunyuan Zhang ,  Hoon Kim ,  Moosung M. Chae

IPC分类号： H01L21/768 ,  H01L23/482 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture in an interlayer dielectric. A seed layer is formed in the aperture, where the seed layer includes manganese and copper, and where the seed layer has a copper concentration gradient. A core is formed overlying the seed layer, where the core includes copper.

摘要翻译： 提供了具有铜和镁组件的集成电路以及用于制造这种集成电路的方法。 集成电路的制造方法包括在层间电介质中形成孔。 在孔中形成种子层，其中种子层包括锰和铜，并且其中种子层具有铜浓度梯度。 核心覆盖种子层，其中核心包括铜。

公开(公告)号：US20190326209A1

公开(公告)日：2019-10-24

申请号：US15959727

申请日：2018-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L23/528 ,  H01L23/525 ,  H01L21/768

摘要： Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20180033728A1

公开(公告)日：2018-02-01

申请号：US15221647

申请日：2016-07-28

申请人： GLOBALFOUNDRIES INC.

发明人： Xunyuan Zhang ,  Moosung M. Chae

IPC分类号： H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76804 ,  H01L21/76883 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0883 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568

摘要： Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a conductive region, and an inter-level dielectric (ILD) material positioned on the conductive region, wherein the ILD material includes a contact opening to the conductive region; forming a doped metal layer within the contact opening such that the doped metal layer overlies the conductive region, wherein the doped metal layer includes a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material.

公开(公告)号：US09484297B2

公开(公告)日：2016-11-01

申请号：US14656770

申请日：2015-03-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Ki Young Lee ,  Moosung M. Chae ,  Woo Sik Kim

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L49/02

CPC分类号： H01L23/5227 ,  H01L21/02126 ,  H01L21/02362 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L28/10

摘要： Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench.

摘要翻译： 提供具有单芯电感器的集成电路及其制造方法。 实施例包括在电介质层中形成沟槽; 通过在所述电介质层上设置金属硬掩模和氧化物硬掩模，并且在所述沟槽中以条状形成第一金属氧化物硬掩模; 通过所述第一金属氧化物硬掩模形成金属线沟槽并进入所述电感器沟槽和第一通孔的相对侧上的第一介电层; 填充第一金属线沟槽，第一通孔和沟槽; 在填充的沟槽上形成另一介电层和第二金属氧化物硬掩模; 通过第二金属氧化物硬掩模形成第二沟槽并形成第二介电层和第二金属线沟槽和第二通孔; 以及填充第二金属线沟槽，第二通孔和第二沟槽。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC分类号： H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC分类号： H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

摘要： A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

摘要翻译： 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

公开(公告)号：US10784195B2

公开(公告)日：2020-09-22

申请号：US15959727

申请日：2018-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/525

摘要： Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US10553478B2

公开(公告)日：2020-02-04

申请号：US16049303

申请日：2018-07-30

申请人： GLOBALFOUNDRIES INC.

发明人： Xunyuan Zhang ,  Moosung M. Chae

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

摘要： Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.