公开(公告)号：US20240147736A1

公开(公告)日：2024-05-02

申请号：US17974028

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Alexander Derrickson ,  Hongru Ren

IPC: H01L27/24 ,  H01L23/48 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L23/481 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/16

Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.

公开(公告)号：US20230131403A1

公开(公告)日：2023-04-27

申请号：US17452175

申请日：2021-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： David C. Pritchard ,  Hongru Ren ,  Zhixing Zhao

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure including a gate structure over a semiconductor layer. The gate structure includes a first portion having a first horizontal width, and a second portion laterally adjacent the first portion and having a second horizontal width less than the first horizontal width. A gate contact is on the first portion of the gate structure and is not on the second portion of the gate structure.

公开(公告)号：US20220285274A1

公开(公告)日：2022-09-08

申请号：US17194565

申请日：2021-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hongru Ren ,  David Pritchard ,  Ryan W. Sporer ,  Manjunatha Prabhu

IPC: H01L23/535 ,  H01L27/12 ,  H01L21/74

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.