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公开(公告)号：US20210242316A1
公开(公告)日：2021-08-05
申请号：US16776711
申请日：2020-01-30
发明人： Heng Yang , David Pritchard , Kai Sun , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
IPC分类号： H01L29/417 , H01L29/16 , H01L29/08 , H01L29/78 , H01L29/66
摘要： One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.
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公开(公告)号：US20210242094A1
公开(公告)日：2021-08-05
申请号：US16776636
申请日：2020-01-30
发明人： Heng Yang , David Pritchard , Kai Sun , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
IPC分类号： H01L21/8238
摘要： One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.
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公开(公告)号：US11610843B2
公开(公告)日：2023-03-21
申请号：US17194565
申请日：2021-03-08
发明人： Hongru Ren , David Pritchard , Ryan W. Sporer , Manjunatha Prabhu
IPC分类号： H01L23/535 , H01L21/74 , H01L27/12
摘要： An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.
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公开(公告)号：US11094791B1
公开(公告)日：2021-08-17
申请号：US16776711
申请日：2020-01-30
发明人： Heng Yang , David Pritchard , Kai Sun , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
摘要： One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.
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5.发明公开公开(公告)号：US20230147981A1
公开(公告)日：2023-05-11
申请号：US18149239
申请日：2023-01-03
发明人： David Pritchard , Heng Yang , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
CPC分类号： H01L29/7606 , H01L29/0847 , H01L29/1033
摘要： A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
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公开(公告)号：US11581430B2
公开(公告)日：2023-02-14
申请号：US16548518
申请日：2019-08-22
发明人： David Pritchard , Heng Yang , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
摘要： A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
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公开(公告)号：US11239087B2
公开(公告)日：2022-02-01
申请号：US16662091
申请日：2019-10-24
发明人： Heng Yang , David C. Pritchard , George J. Kluth , Anurag Mittal , Hongru Ren , Manjunatha G. Prabhu , Kai Sun , Neha Nayyar , Lixia Lei
IPC分类号： H01L27/12 , H01L21/308 , H01L21/84 , H01L29/66 , H01L29/78 , H01L21/311 , H01L21/02
摘要： The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
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公开(公告)号：US11177182B2
公开(公告)日：2021-11-16
申请号：US16776636
申请日：2020-01-30
发明人： Heng Yang , David Pritchard , Kai Sun , Hongru Ren , Neha Nayyar , Manjunatha Prabhu , Elizabeth Strehlow , Salvatore Cimino
IPC分类号： H01L29/66 , H01L21/8238
摘要： One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.
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公开(公告)号：US20240194535A1
公开(公告)日：2024-06-13
申请号：US18080017
申请日：2022-12-13
发明人： Venkatesh P. Gopinath , Navneet Jain , Hongru Ren , Alexander Derrickson , Jianwei Peng , Bipul C. Paul
IPC分类号： H01L21/8234 , H01L21/768 , H01L29/423 , H01L29/49 , H10B63/00
CPC分类号： H01L21/823475 , H01L21/76895 , H01L29/42316 , H01L29/4933 , H10B63/34
摘要： Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.
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公开(公告)号：US20240162090A1
公开(公告)日：2024-05-16
申请号：US17985487
申请日：2022-11-11
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L27/092
CPC分类号： H01L21/76897 , H01L21/823871 , H01L23/5226 , H01L23/528 , H01L27/092
摘要： Structures with features formed by self-aligned double patterning and methods of self-aligned multiple patterning. The structure comprises a first field-effect transistor including a first gate and a first protrusion projecting laterally from the first gate, and a second field-effect transistor including a second gate and a second protrusion projecting laterally from the second gate. The second gate and the second protrusion are spaced in a lateral direction from the first gate and the first protrusion. The structure further comprises a gate contact connecting the first protrusion of the first gate to the second protrusion the second gate.
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