中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.019 seconds)

    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS
    1.
    发明公开
    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS 审中-公开

    公开(公告)号：US20240221810A1

    公开(公告)日：2024-07-04

    申请号：US18607725

    申请日：2024-03-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C11/22

    CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

    Partitioned memory architecture with single resistor or dual resistor memory elements for in-memory pipeline processing
    3.
    发明授权
    Partitioned memory architecture with single resistor or dual resistor memory elements for in-memory pipeline processing 有权

    公开(公告)号：US12125530B2

    公开(公告)日：2024-10-22

    申请号：US18045524

    申请日：2022-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C13/00 ,  G11C11/16 ,  G11C27/02

    CPC classification number: G11C13/0026 ,  G11C11/1655 ,  G11C13/0004 ,  G11C13/0038 ,  G11C27/02

    Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

    Partitioned memory architecture with dual resistor memory elements for in-memory serial processing
    4.
    发明授权
    Partitioned memory architecture with dual resistor memory elements for in-memory serial processing 有权

    公开(公告)号：US12106804B2

    公开(公告)日：2024-10-01

    申请号：US18045479

    申请日：2022-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004

    Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements, each including first and second programmable resistors having inputs connected to an input node and outputs connected to first and second bitlines. In each bank, first and second feedback buffers are connected to the first and second bitlines and first and second output nodes. First and second output nodes of banks in the same column are connected to the same first and second column interconnect lines. The initial bank in each row includes amplifiers connected between the input nodes and memory elements. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

    Structure including a cross-bar router and method
    5.
    发明授权
    Structure including a cross-bar router and method 有权

    公开(公告)号：US12027226B2

    公开(公告)日：2024-07-02

    申请号：US17810018

    申请日：2022-06-30

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Navneet K. Jain ,  Sven Beyer

    IPC: G11C16/04 ,  G11C5/06 ,  G11C11/22 ,  G11C13/00

    CPC classification number: G11C5/063 ,  G11C11/22 ,  G11C13/0028 ,  G11C13/0069

    Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

    CALIBRATION METHODS AND STRUCTURES FOR PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESISTOR MEMORY ELEMENTS
    6.
    发明公开
    CALIBRATION METHODS AND STRUCTURES FOR PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESISTOR MEMORY ELEMENTS 审中-公开

    公开(公告)号：US20240119974A1

    公开(公告)日：2024-04-11

    申请号：US18045529

    申请日：2022-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C7/10 ,  G11C7/12 ,  G11C13/00

    CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/12 ,  G11C13/0069

    Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS
    8.
    发明公开
    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS 审中-公开

    公开(公告)号：US20230260561A1

    公开(公告)日：2023-08-17

    申请号：US17671652

    申请日：2022-02-15

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C11/22

    CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

    Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements
    10.
    发明授权
    Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements 有权

    公开(公告)号：US12136468B2

    公开(公告)日：2024-11-05

    申请号：US18045529

    申请日：2022-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C7/10 ,  G11C7/12 ,  G11C13/00

    Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

Patent Agency Ranking