公开(公告)号：US20190204753A1

公开(公告)日：2019-07-04

申请号：US16325319

申请日：2017-12-01

Applicant: Google LLC

Inventor： Brian James Burkett ,  Rami Barends

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/70 ,  G03F1/76

CPC classification number: G03F7/70425 ,  G03F1/36 ,  G03F1/70 ,  G03F1/76

Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

公开(公告)号：US12239027B2

公开(公告)日：2025-02-25

申请号：US18117918

申请日：2023-03-06

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H10N60/01 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US20240194661A1

公开(公告)日：2024-06-13

申请号：US18080729

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/81 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/81815

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20240194532A1

公开(公告)日：2024-06-13

申请号：US18080715

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L21/8221 ,  H01L21/02505 ,  H01L21/02598 ,  H01L21/31127 ,  H01L21/7688 ,  H01L24/16 ,  H01L24/29 ,  H01L25/074 ,  B82Y10/00

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20220328749A1

公开(公告)日：2022-10-13

申请号：US17836893

申请日：2022-06-09

Applicant: Google LLC

Inventor： Brian James Burkett

IPC: H01L39/24 ,  G06N10/00 ,  B82Y10/00

Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.

公开(公告)号：US11378890B2

公开(公告)日：2022-07-05

申请号：US17208391

申请日：2021-03-22

Applicant: Google LLC

Inventor： Brian James Burkett ,  Rami Barends

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/70 ,  G03F1/76

Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

公开(公告)号：US20210336121A1

公开(公告)日：2021-10-28

申请号：US16964053

申请日：2019-07-25

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H01L39/24 ,  H01L39/02 ,  H01L39/22 ,  G06N10/00

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US20210208509A1

公开(公告)日：2021-07-08

申请号：US17208391

申请日：2021-03-22

Applicant: Google LLC

Inventor： Brian James Burkett ,  Rami Barends

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/70 ,  G03F1/76

Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.