公开(公告)号：US07966457B2

公开(公告)日：2011-06-21

申请号：US11928322

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

IPC分类号： G06F12/14

CPC分类号： G06F12/126 ,  G06F12/0862 ,  G06F2212/2022 ,  G06F2212/6022

摘要： A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

摘要翻译： 用于中央处理单元的高速缓存模块具有与存储器耦合的高速缓存控制单元和与控制单元和存储器耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存线，每条高速缓存行具有存储区域 要顺序地发出的指令和关联的控制位，其中多个高速缓存行中的至少一个高速缓存行具有至少一个分支跟踪控制位，当至少一个分支跟踪控制位在预定义的分支指令具有的情况下提供高速缓存行的自动锁定功能时 已发出。

公开(公告)号：US06976158B2

公开(公告)日：2005-12-13

申请号：US09870451

申请日：2001-06-01

申请人： Michael Catherwood ,  Joseph W. Triece

发明人： Michael Catherwood ,  Joseph W. Triece

IPC分类号： G06F9/32 ,  G06F9/44 ,  G06F9/48 ,  G06F13/32

CPC分类号： G06F9/30065

摘要： A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruction may include an address of a register which holds the loop count value. The instruction immediately following the repeat instruction is the target instruction for repetition. The processing includes repeating execution of the target instruction according to the loop count value in a low processor cycle overhead manner. The processing may also include handling interrupts during repeat instruction processing in a low-overhead manner during the initial call of the interrupt service routine as well as upon returning from the interrupt service routine.

摘要翻译： 提供了一种处理可中断重复指令的处理器。 重复指令可以包括指定与循环要重复的次数相对应的循环计数值的立即操作数。 或者，重复指令可以包括保存循环计数值的寄存器的地址。 重复指令之后的指令是重复的目标指令。 该处理包括以低处理器周期开销方式根据循环计数值重复执行目标指令。 处理还可以包括在中断服务程序的初始调用期间以及从中断服务程序返回时以低开销方式在重复指令处理期间处理中断。

公开(公告)号：US06321319B2

公开(公告)日：2001-11-20

申请号：US09756304

申请日：2001-01-08

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

公开(公告)号：US5905880A

公开(公告)日：1999-05-18

申请号：US937682

申请日：1997-09-29

申请人： Rodney J. Drake ,  Joseph W. Triece

发明人： Rodney J. Drake ,  Joseph W. Triece

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30069 ,  G06F9/30149

摘要： An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.

摘要翻译： 具有鲁棒多字指令的微控制器指令集。 指令集具有多个指令，其中多个指令包括单字指令和多个字指令。 至少一个位位于所有多个字指令的所有非首字中的预定位置。 如果在多字指令中执行任何后续字之前未执行多字指令的第一个字，该位将被微控制器解码为无操作位。

公开(公告)号：US08650356B2

公开(公告)日：2014-02-11

申请号：US12776046

申请日：2010-05-07

申请人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

发明人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

IPC分类号： G06F15/16

CPC分类号： H04L12/40013 ,  H04L12/4135 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/40215

摘要： A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.

摘要翻译： 微控制器具有随机存取存储器和控制器区域网络（CAN）控制器，控制单元接收组合的CAN消息。 控制单元使用组合的CAN消息生成缓冲器描述符表条目，并将缓冲器描述符表条目存储在随机存取存储器中，并且缓冲器描述符表条目至少具有来自CAN消息的消息标识符和加载数据，以及 跟随缓冲区描述符表项。

公开(公告)号：US08650341B2

公开(公告)日：2014-02-11

申请号：US12758448

申请日：2010-04-12

申请人： Steven G. Dawson ,  Tim L. Wilson ,  Joseph W. Triece

发明人： Steven G. Dawson ,  Tim L. Wilson ,  Joseph W. Triece

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： H04L12/413 ,  H04L49/90

摘要： A controller area network (CAN) controller unit has a message assembly buffer receiving a serial bitstream, a buffer memory coupled in parallel with said message assembly buffer, a CAN control unit coupled with the message assembly and the buffer memory, and at least one control register. The at least one control register can be programmed to cause the CAN control unit to store a message received in the message assembly register in at least a first and second mode, wherein in the first mode, control information and data payload of the received CAN message are stored in the buffer memory and in the second mode only the data payload of the CAN message is stored in the buffer memory.

摘要翻译： 控制器区域网络（CAN）控制器单元具有接收串行比特流的消息组合缓冲器，与所述消息组合缓冲器并行耦合的缓冲存储器，与消息组件和缓冲存储器耦合的CAN控制单元，以及至少一个控制器 寄存器。 至少一个控制寄存器可以被编程为使得CAN控制单元至少存储第一和第二模式中的消息组合寄存器中接收到的消息，其中在第一模式中，所接收的CAN消息的控制信息和数据净荷 被存储在缓冲存储器中，并且在第二模式中，只有CAN消息的数据有效载荷被存储在缓冲存储器中。

公开(公告)号：US07788434B2

公开(公告)日：2010-08-31

申请号：US11928212

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Joseph W. Triece

IPC分类号： G06F13/24 ,  G06F13/26

CPC分类号： G06F13/26

摘要： An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

摘要翻译： 中断控制器具有接收多个中断源信号的中断寄存器单元，耦合到中断寄存器单元的中断检测器，耦合到中断检测器的计数单元，其中在第一次发生中断源信号时，该计数器单元定义一个 时间窗口，其中中断寄存器存储进一步的中断源信号，以及中断请求单元，其耦合到计数器单元以产生中断请求信号。

公开(公告)号：US20080147946A1

公开(公告)日：2008-06-19

申请号：US11928212

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Joseph W. Triece

IPC分类号： G06F13/24

CPC分类号： G06F13/26

摘要： An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

摘要翻译： 中断控制器具有接收多个中断源信号的中断寄存器单元，耦合到中断寄存器单元的中断检测器，耦合到中断检测器的计数单元，其中在第一次发生中断源信号时，该计数器单元定义一个 时间窗口，其中中断寄存器存储进一步的中断源信号，以及中断请求单元，其耦合到计数器单元以产生中断请求信号。

公开(公告)号：US06463544B2

公开(公告)日：2002-10-08

申请号：US09850214

申请日：2001-05-07

申请人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

发明人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC分类号： G06F126

CPC分类号： G11C5/14 ,  G11C7/1045 ,  H03K19/0016

摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

摘要翻译： 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

公开(公告)号：US06243798B1

公开(公告)日：2001-06-05

申请号：US08958940

申请日：1997-10-28

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

摘要翻译： 用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。 第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。 指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。 提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。 第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上 地址总线 这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。