公开(公告)号：US06321319B2

公开(公告)日：2001-11-20

申请号：US09756304

申请日：2001-01-08

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

公开(公告)号：US5905880A

公开(公告)日：1999-05-18

申请号：US937682

申请日：1997-09-29

申请人： Rodney J. Drake ,  Joseph W. Triece

发明人： Rodney J. Drake ,  Joseph W. Triece

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30069 ,  G06F9/30149

摘要： An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.

摘要翻译： 具有鲁棒多字指令的微控制器指令集。 指令集具有多个指令，其中多个指令包括单字指令和多个字指令。 至少一个位位于所有多个字指令的所有非首字中的预定位置。 如果在多字指令中执行任何后续字之前未执行多字指令的第一个字，该位将被微控制器解码为无操作位。

公开(公告)号：US06243798B1

公开(公告)日：2001-06-05

申请号：US08958940

申请日：1997-10-28

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

摘要翻译： 用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。 第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。 指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。 提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。 第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上 地址总线 这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。

公开(公告)号：US6098160A

公开(公告)日：2000-08-01

申请号：US959559

申请日：1997-10-28

申请人： Rodney J. Drake ,  Randy L. Yach ,  Igor Wojewoda ,  Joseph W. Triece ,  Brian Boles ,  Darrel Johansen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Igor Wojewoda ,  Joseph W. Triece ,  Brian Boles ,  Darrel Johansen

IPC分类号： G06F9/35 ,  G06F12/00

CPC分类号： G06F9/35

摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

摘要翻译： 一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。 数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。 数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。 增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。 加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。 多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

公开(公告)号：US09208095B2

公开(公告)日：2015-12-08

申请号：US11928242

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。

公开(公告)号：US20100306457A1

公开(公告)日：2010-12-02

申请号：US12776046

申请日：2010-05-07

申请人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

发明人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

IPC分类号： G06F15/16 ,  G06F12/02

CPC分类号： H04L12/40013 ,  H04L12/4135 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/40215

摘要： A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.

摘要翻译： 微控制器具有随机存取存储器和控制器区域网络（CAN）控制器，控制单元接收组合的CAN消息。 控制单元使用组合的CAN消息生成缓冲器描述符表条目，并将缓冲器描述符表条目存储在随机存取存储器中，并且缓冲器描述符表条目至少具有来自CAN消息的消息标识符和加载数据，以及 跟随缓冲区描述符表项。

公开(公告)号：US07603601B2

公开(公告)日：2009-10-13

申请号：US11355619

申请日：2006-02-16

申请人： Cristian P. Masgras ,  Michael Pyska ,  Edward Brian Boles ,  Joseph W. Triece ,  Igor Wojewoda ,  Mei-Ling Chen

发明人： Cristian P. Masgras ,  Michael Pyska ,  Edward Brian Boles ,  Joseph W. Triece ,  Igor Wojewoda ,  Mei-Ling Chen

IPC分类号： G01R31/3185

CPC分类号： G01R31/31701 ,  G06F11/273 ,  G11C29/003 ,  G11C29/46

摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

摘要翻译： 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。 特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。

公开(公告)号：US20080147979A1

公开(公告)日：2008-06-19

申请号：US11928242

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。

公开(公告)号：US06563740B2

公开(公告)日：2003-05-13

申请号：US09951280

申请日：2001-09-13

申请人： Joseph A. Thomsen ,  Mitchel Obolsky ,  Joseph W. Triece

发明人： Joseph A. Thomsen ,  Mitchel Obolsky ,  Joseph W. Triece

IPC分类号： G11C1134

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C16/3418 ,  G11C29/50

摘要： An electronic circuit includes a non-volatile memory on an integrated circuit that has several memory cells. The cells each have a voltage state and a gate. A gate bias circuit on the integrated circuit is coupled to the gates of the memory cells. The gate bias circuit includes at least a read voltage and a margin voltage. A detection circuit on the integrated circuit is coupled to the cells. The detection circuit includes a comparator and a reference voltage. The reference voltage and the voltage state of one of the cells are coupled to the comparator. The detection circuit includes an output generating a signal corresponding to the comparator output. The integrated circuit includes a monitor circuit. The monitor circuit is coupled to the output of the detection circuit and determines whether the voltage state of the cell transitions between application of the read and margin voltages to the gate.

公开(公告)号：US06230275B1

公开(公告)日：2001-05-08

申请号：US09232053

申请日：1999-01-15

申请人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

发明人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC分类号： G06F126

CPC分类号： G11C5/14 ,  G11C7/1045 ,  H03K19/0016

摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

摘要翻译： 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。