公开(公告)号：US06278724B1

公开(公告)日：2001-08-21

申请号：US09032776

申请日：1998-03-06

申请人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Xuping Zhou ,  Xiaoling Qin ,  Jie Chen ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Xuping Zhou ,  Xiaoling Qin ,  Jie Chen ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H04L2732

CPC分类号： H04B1/7113 ,  H04B1/7117 ,  H04B1/712 ,  H04B1/7183

摘要： A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks. A rake combiner synchronously combines the phase-corrected de-spread received signals of each path.

摘要翻译： 扩频通信系统中的信号接收装置仅需要少量的电路并消耗少量的电力。 正交检测器将接收信号分解为同相分量和正交分量，并将其提供给复合型匹配滤波器。 复合型匹配滤波器对同相分量和正交分量进行解扩，并将它们发送到多路径选择器。 多径选择器从接收到的解扩信号中选择具有高电平信号电功率的多个路径，并将所选择的路径的接收信号发送到多个相位校正块。 模拟运算电路计算每个路径的两个连续导频符号块的接收信号的相位误差。 模拟运算电路校正在两个连续的导频符号块之间已经接收到的信息符号块的接收信号的相位。 瑞克组合器同步地组合每个路径的相位校正的去扩展接收信号。

公开(公告)号：US5974038A

公开(公告)日：1999-10-26

申请号：US864784

申请日：1997-05-29

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04L7/00 ,  H04B7/216

CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

摘要： This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.

摘要翻译： 本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。 接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。 该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。 当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号 。 此外，进行解扩。 来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

公开(公告)号：US5930290A

公开(公告)日：1999-07-27

申请号：US841217

申请日：1997-04-30

申请人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

发明人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04J13/10 ,  H04B15/00 ,  H04B7/216

CPC分类号： H04J13/0077 ,  H04B1/7093

摘要： A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.

摘要翻译： 提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。 要发送的一系列数字数据被分为4位帧。 每帧的4位数据按预定顺序分成第一至第四元素。 第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。 要传输的数据的频谱通过乘以这些复数来传播。 四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。 根据匹配滤波器的输出，恢复第一至第四元件。

公开(公告)号：US5872466A

公开(公告)日：1999-02-16

申请号：US686950

申请日：1996-07-26

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03H11/04 ,  H03H17/02 ,  H04B1/707 ,  H04B1/7093 ,  H04L7/00 ,  H04L7/10 ,  H03K5/00

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

摘要翻译： 公开了具有降低的电力消耗的匹配滤波器。 由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。 由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。 各组中的信号通过电容耦合并联并且在电路中间歇地供电。

公开(公告)号：US5783961A

公开(公告)日：1998-07-21

申请号：US764637

申请日：1996-12-11

申请人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03K19/0948 ,  H03F1/02 ,  H03F1/34 ,  H03F3/46 ,  H03F3/72 ,  H03K5/153 ,  H03H11/26

CPC分类号： H03F3/72

摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

摘要翻译： 本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。 在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。 当反相放大电路不工作时，MOS开关打开。

公开(公告)号：US06169771A

公开(公告)日：2001-01-02

申请号：US09014264

申请日：1998-01-27

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04L2706

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.

摘要翻译： 一方面，本发明提供一种低功耗匹配滤波器。 在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。 另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。 输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。 正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。 加法电路以相同的方式刷新。

公开(公告)号：US5737368A

公开(公告)日：1998-04-07

申请号：US715321

申请日：1996-09-17

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04J13/00 ,  G11C27/02 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H03D1/00

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： A matched filter contains a plurality of auxiliary sampling and holding circuits in addition to a main sampling and holding circuit containing multiple unit sampling and holding circuits. An auxiliary sampling and holding circuit is used to hold an input voltage, which would ordinarily be held by a unit sampling and holding circuit, when the unit sampling and holding circuit is being refreshed. By holding a part of the analog input voltage in the auxiliary sampling and holding circuits, refreshing is performed without decreasing the overall calculation speed.

摘要翻译： 除了包含多个单元采样和保持电路的主采样和保持电路之外，匹配滤波器还包含多个辅助采样和保持电路。 当单元采样和保持电路被刷新时，辅助采样和保持电路用于保持通常由单元采样和保持电路保持的输入电压。 通过将模拟输入电压的一部分保持在辅助采样和保持电路中，在不降低总体计算速度的情况下执行刷新。

公开(公告)号：US5841315A

公开(公告)日：1998-11-24

申请号：US686958

申请日：1996-07-26

申请人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03M1/66 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H03M3/02 ,  H03K5/00 ,  G11C27/02 ,  H03K12/00

CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254 ,  H04B1/7117

摘要： An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

摘要翻译： 本发明的目的是提供一种尺寸小且消耗低功率的匹配滤波电路。 注意扩展码是1位数据串，输入信号被采样并保持为沿着时间序列的模拟信号，分为“1”和“-1”，分类信号通过电容耦合并联 在根据本发明的匹配滤波器电路中。

公开(公告)号：US5958002A

公开(公告)日：1999-09-28

申请号：US905784

申请日：1997-08-12

申请人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： G06G7/25 ,  G06G7/22 ,  G06G7/00 ,  G06G7/16

CPC分类号： G06G7/22

摘要： A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##

摘要翻译： 高精度矢量绝对值计算电路采用模拟处理和最小硬件。 对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及 它们都被转换为绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值 通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。 从输出端子27输出由下式计算的复数绝对值。

公开(公告)号：US5815021A

公开(公告)日：1998-09-29

申请号：US686761

申请日：1996-07-26

申请人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： G06G7/14 ,  G06J1/00 ,  G06G7/16

CPC分类号： G06J1/00 ,  G06G7/14

摘要： The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

摘要翻译： 本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。 在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。 在电容耦合中保持电压并加上重量。